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TSMC 2nm Process Disclosure – How Does It Measure Up?

semiwiki.com

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#11

Earlier quoted context omitted.

I think that this graph sums it up pretty precisely: https://semiwiki.com/wp-content/uploads/2025/02/Figure-1.jpg > You see, the bars go up and to the right as indicated by the arrow. The thing at the top right, which is under discussion, is more than fifteen times better than the thing on the bottom left. This is a huge achievement.

I know you’re joking but that graph is spurious: > We took the graph image, pulled it into Excel and created an Excel graph overlaying it with the 28nm bar normalized to 1 and then entering values for the other bars until they matched the graph. If we then build a set of bars starting at 28nm = 1 scaled up based on the TSMC announced node to node power improvements we get a total improvement of less than 9x. Nodes fr…

Not sure if if this is way overblown in my head but this society, domain, and economy don't take asymptotic progress for an ok answer, and always have the pressure to deliver ever increasing performances and results, even when the law of physics become harder and harder to bend or circumvent.

It shouldn't limit innovation and trying to go past those limits one way or another, but at some point it feels like marginal (or below expectations) progress isn't acceptable at least for a while. That it then has to become coated in some marketing lie or half-truths to mask reality and oversell what it truly is... That's still progress! And it can slow down, accelerate, who knows? This should be acceptable.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#12
Is there an advantage on going 2nm given the costs? Maybe somebody can clearly answer this here on HN, I love this subject!

It's interesting how the whole valuation of TSMC(and some from NVidia) are aligned by their current advantage on the 3nm process.

Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat.

It's definitely what they need to get them back into the processor game and beat everybody, maybe we will see Apple doing designs with the Intel factory before 2030?

Hope they don't fail their deadlines: summer this year to be producing 18A, and 2026 mass production.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#13
post #10

Super interesting. Now what we really need is for Raspberry Pi to make a 2nm version so that the power usage becomes more acceptable for Wildlife and biodiversity use cases. Please, please Raspberry Pi, also make a 2nm version Actually, I think it's broadcom I need to ask that from isn't it ? (Although then I think it would almost become a Jetson) Please please NVidia make a 1nm Jetson, the planet needs you to.

The current Pi 5 is on a 16nm node[1], down from 28nm for the Pi 4.

So, far off needing a bleeding edge node[2] to see further improvements.

[1]: https://chipwise.tech/our-portfolio/raspberry-pi-5/

[2]: https://www.tsmc.com/english/dedicatedFoundry/technology/log...

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#14

Is there an advantage on going 2nm given the costs? Maybe somebody can clearly answer this here on HN, I love this subject! It's interesting how the whole valuation of TSMC(and some from NVidia) are aligned by their current advantage on the 3nm process. Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. It's definitely what they need…

For datacenters and especially hyperscalers, the power and cooling bill is a huge part of the TCO.

You make somewhat more power efficient chips, you get to sell it for a lot more.

Your chips are inefficient, and you won’t be able to sell to a hyperscaler even for $0.

The latter is the position Intel is quickly arriving at for DC; Epycs are much more efficient and Intel’s wildly slashing prices.

For Apple, A-series dies are pretty small, they basically prefund a large part of TSMC and almost certainly gets the lowest prices of any customer.

That said, Apple’s strict fascination with always jumping to the latest node, even when it seems premature, puzzles me from the outside.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#17
post #10

Super interesting. Now what we really need is for Raspberry Pi to make a 2nm version so that the power usage becomes more acceptable for Wildlife and biodiversity use cases. Please, please Raspberry Pi, also make a 2nm version Actually, I think it's broadcom I need to ask that from isn't it ? (Although then I think it would almost become a Jetson) Please please NVidia make a 1nm Jetson, the planet needs you to.

[deleted]

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#18

Is there an advantage on going 2nm given the costs? Maybe somebody can clearly answer this here on HN, I love this subject! It's interesting how the whole valuation of TSMC(and some from NVidia) are aligned by their current advantage on the 3nm process. Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. It's definitely what they need…

>Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat.

That's a pretty serious abuse of the word "literally" given that they have nothing in common except vague density figures which don't mean that much at this point.

Here's a line literally from the article

>Based on this analysis it is our belief that Intel 18A has the highest performance for a 2nm class process with TSMC in second place and Samsung in third place.

Given what we currently know about 18A, Intel's process appears to be less dense but with a higher emphasis on performance, which is in line with recent Intel history. Just looking at the density of a process won't tell you everything about it. If density were everything then Intel's 14nm++++ chips wouldn't have managed to remain competitive in raw performance for so many years against significantly denser processes. Chip makers have a bunch of parameters they have to balance when designing new nodes. This has only gotten more important as node shrinks have become more difficult. TSMC has always leaned more towards power efficiency, largely because their rise to dominance was driven by mobile focused chips. Intel's processes have always prioritized performance more as more of their products are plugged into the wall. Ideally, you want both but R&D resources are not unlimited.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#19

How much would the Non-Recurrent Cost associated with designing a RISC-V CPU using this 2nm? EDA Tools, Photo-Masks, One Time Chip Design Engineer Cost, Simulation/Virtual Verification and so on. I mean every thing till tape-out.

3nm was over a half billion. So if costs are going up at the same rate, over a billion dollars.

https://semianalysis.com/2022/07/24/the-dark-side-of-the-sem...

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#20

Is there an advantage on going 2nm given the costs? Maybe somebody can clearly answer this here on HN, I love this subject! It's interesting how the whole valuation of TSMC(and some from NVidia) are aligned by their current advantage on the 3nm process. Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. It's definitely what they need…

>Intel on 18A is literally TSMC's 3nm process + backside power delivery, which means more power efficiency, performance also less heat. That's a pretty serious abuse of the word "literally" given that they have nothing in common except vague density figures which don't mean that much at this point. Here's a line literally from the article >Based on this analysis it is our belief that Intel 18A has the highest perform…

The death of Dennard scaling means that power efficiency is king, because a more power efficient chip is also a chip that can keep more of its area powered up over time for any given amount of cooling - which is ultimately what matters for performance. This effect becomes even more relevant as node sizes decrease and density increases.
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