What is the speed of a Xilinux Spartan 6 compared to an recent Intel i5-i7 series cpu?
What is the cruising altitude of a Boeing 787 compared to a VW beetle?
You cannot compare these things in this way, it's apples and oranges.
An open source Xilinx Spartan 6 miniPCIe development board
41–46 of 46 posts
Re: An open source Xilinx Spartan 6 miniPCIe development board
#42Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?
This. Although I think Altium is the more offensive toolset. The real fly in the ointment for open source hardware is the proprietary tooling.
Altium have recently released 'circuitmaker' which is basically a $0 version of Altium, for open hardware. I guess it's meant to compete with Eagle, which a lot of open hardware projects use.
It's still closed source (like Eagle). And it's Windows-only. And currently there's a DirectX conflict with VirtualBox so you can't use it there (reportedly it works in other VMs). But it's cheaper than paying $9000-a-seat-plus-$1000-a-year-maintainance for commercial Altium.
Re: An open source Xilinx Spartan 6 miniPCIe development board
#43Earlier quoted context omitted.
This. Although I think Altium is the more offensive toolset. The real fly in the ointment for open source hardware is the proprietary tooling.
I've since moved on to KiCAD and been pretty happy with it. Something like this board would still be near difficult to impossible, though, as impedance matching for the DDR lines doesn't really exist in KiCAD. I also ordered a few ICEsticks to play with the new icestorm open source toolchain. That FPGA is in no way comparable to a Spartan 6, though.
New KiCAD versions (from bzr) have push and shove interactive router which also can do length matching and differential pairs, although the whole thing is far from complete and stable but it is usable (for example, the "push and shove" part does not work when routing diff pairs and when you move move mouse too fast in plain track routing mode it just crashes).
One problem with these new features is that they are somehow linked to new implementation of pcbnew's canvas which also implies somewhat different UI behavior (more windows-like, with selection of individual PCB elements and so on), which I generally don't like that much. Anyhow I recently used current kicad from bzr for somewhat non-trivial board (smallish FPGA in TQFP, ARM MCU, some analog RF, few LVDS lines).
Re: An open source Xilinx Spartan 6 miniPCIe development board
#44Earlier quoted context omitted.
So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?
Ugh, that time window. I once had to work with a hardware team to debug a "boot issue" where we were right on the margin due to a two-phase boot process (boot initial bitstream, check journal in flash, load active bitstream) and didn't even realize going into the debugging that we were close to the margin. It's nice to be doing plain-old software again...
Which platforms are the most demanding regarding PCIe time window? Which ones caused you problems?
Re: An open source Xilinx Spartan 6 miniPCIe development board
#45Earlier quoted context omitted.
Supposedly, a lot of key FPGA patents are set to expire Real Soon Now, or just did, or something along those lines. I'm holding out hope that we'll have a true Open Source FPGA environment sooner or later, but it sure is taking it's time... :-(
Are patents really what's blocking it? I only have a passing understanding of the FPGA world, but I thought that everything in that space in shrouded in trade secrets. Do patent claim descriptions really have enough detail to help you produce a working bitstream?
> Are patents really what's blocking it?
Honestly, I'm far from an expert on this topic, but I've heard quite a few people who play in this space more than I do, speak of the patent issue as being one important blocker. My guess is that patents are just one of multiple factors. What, exactly, it would take to get a full Open Source FPGA toolchain, I don't know. But some of the other answers in this thread are full of very illuminating info, so I'm kinda glad this came up. I've learned a lot just from reading the other responses.
Re: An open source Xilinx Spartan 6 miniPCIe development board
#46Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?
Another possible application: talking to high speed serial busses. This isn't just a Spartan 6, it's a Spartan 6 XCblahblahT. Usually when you see cheap Spartan 6 boards they use the non-transceiver version to cut costs without mentioning that it cuts one of the killer features of the chip! This one is the real deal. You still have to use ISE (not even Vivado; they locked the Spartan 6s out of Vivado) but it's still…
This is MiniPCIe which would only have a x1 connection to the edge fingers, which means only 4 GTP connections would be needed (and the XC6SLX100T has 8 IIRC).