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An open source Xilinx Spartan 6 miniPCIe development board

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Re: An open source Xilinx Spartan 6 miniPCIe development board

#11

Post by aceperry »

TD-Linux wrote: post #3

Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?

This. Although I think Altium is the more offensive toolset. The real fly in the ointment for open source hardware is the proprietary tooling.

Re: An open source Xilinx Spartan 6 miniPCIe development board

#12

Post by vardump »

duskwuff wrote: post #8
vardump wrote: post #4

So there's a serial flash on board? How many milliseconds max it takes to load the bitstream to FPGA after power on? Can you load PCIe endpoint within PCIe spec alotted time, 100 ms? Is partial bitstream reprogramming possible?

The FPGA is an XC6SLX100T, so the bitstream could be up to 26.7 megabits. It could take up to two seconds or so to configure the part with a large design.

So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?

Re: An open source Xilinx Spartan 6 miniPCIe development board

#13

Post by Sanddancer »

vardump wrote: post #12
duskwuff wrote: post #8

Earlier quoted context omitted.

The FPGA is an XC6SLX100T, so the bitstream could be up to 26.7 megabits. It could take up to two seconds or so to configure the part with a large design.

So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?

Yes. Xilinx chips can do on-the-fly reconfiguration. So you can have your bootstrap loader and then either load a more complete firmware from the spi chip, or over pcie

Re: An open source Xilinx Spartan 6 miniPCIe development board

#14

Post by TD-Linux »

aceperry wrote: post #11
TD-Linux wrote: post #3

Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?

This. Although I think Altium is the more offensive toolset. The real fly in the ointment for open source hardware is the proprietary tooling.

I've since moved on to KiCAD and been pretty happy with it. Something like this board would still be near difficult to impossible, though, as impedance matching for the DDR lines doesn't really exist in KiCAD.

I also ordered a few ICEsticks to play with the new icestorm open source toolchain. That FPGA is in no way comparable to a Spartan 6, though.

Re: An open source Xilinx Spartan 6 miniPCIe development board

#15

Post by Sanddancer »

Smushman wrote: post #6

http://polysome.io/ The manufacturer. What purpose is this useful for? Can someone elaborate?

It looks like, from the scant info on the website and github, that they initial goal is to use these as autonomous mesh network nodes, probably with lots of crypto processing, given that the name of the board files is PolysomeCrypto01. It looks, though, like this was discovered before the folks were ready to really discuss it.

Re: An open source Xilinx Spartan 6 miniPCIe development board

#16

Post by mng2 »

TD-Linux wrote: post #3

Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?

It should be mentioned that the '100T device pictured actually requires the full paid version of ISE. The free-as-in-beer ISE Webpack only supports up to the '75T. Thankfully Xilinx implemented compatible packages through the device family, so lower devices are a drop-in replacement (mostly).

Maybe one day we'll have a Free toolchain, but FPGA tools are much closer to chip design tools than to compilers, and the space is fraught with patent concerns. However I did read on Deep Chip that some fundamental synthesis patents have been invalidated, which might open up some breathing room.

Re: An open source Xilinx Spartan 6 miniPCIe development board

#17

Post by mng2 »

Sanddancer wrote: post #13
vardump wrote: post #12

Earlier quoted context omitted.

So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?

Yes. Xilinx chips can do on-the-fly reconfiguration. So you can have your bootstrap loader and then either load a more complete firmware from the spi chip, or over pcie

I don't think it's supported for Spartan-6 though.

Re: An open source Xilinx Spartan 6 miniPCIe development board

#18

Post by vardump »

mng2 wrote: post #17
Sanddancer wrote: post #13

Earlier quoted context omitted.

Yes. Xilinx chips can do on-the-fly reconfiguration. So you can have your bootstrap loader and then either load a more complete firmware from the spi chip, or over pcie

I don't think it's supported for Spartan-6 though.

So it's not possible to implement compliant PCIe interface together with some bigger block with this board?

Re: An open source Xilinx Spartan 6 miniPCIe development board

#19

Post by Sanddancer »

mng2 wrote: post #17
Sanddancer wrote: post #13

Earlier quoted context omitted.

Yes. Xilinx chips can do on-the-fly reconfiguration. So you can have your bootstrap loader and then either load a more complete firmware from the spi chip, or over pcie

I don't think it's supported for Spartan-6 though.

It is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic-partial-reconfigu...
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