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Earlier quoted context omitted.
I don't think it's supported for Spartan-6 though.
It is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic-partial-reconfigu...
KiCad source of the PCIeDuino: https://github.com/moonpunchorg/pcieduino
Pictures: http://imgur.com/a/XiJ12
Really nice design! Impressive routing, I was surprised you were able to fit two DDR chips on there as well. It's still too bad that all the tooling for this is closed source (Altium, Xilinx ISE / Vivado, with the latter being far more offensive). But the Spartan 6 is a really nice chip otherwise. It seems like the target application is compute acceleration. Do you have any particular applications in mind?
It should be mentioned that the '100T device pictured actually requires the full paid version of ISE. The free-as-in-beer ISE Webpack only supports up to the '75T. Thankfully Xilinx implemented compatible packages through the device family, so lower devices are a drop-in replacement (mostly). Maybe one day we'll have a Free toolchain, but FPGA tools are much closer to chip design tools than to compilers, and the spac…
Earlier quoted context omitted.
I don't think it's supported for Spartan-6 though.
It is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic-partial-reconfigu...
When I looked at the encryption format for the virtex 5 series it was quicker to reverse engineer it than it was to find someone within Xilinx that could explain it (just basic bit/byte order, what's covered by encryption, etc).
At the end of the day, FPGA configuration logic is just another state machine ;)
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The FPGA is an XC6SLX100T, so the bitstream could be up to 26.7 megabits. It could take up to two seconds or so to configure the part with a large design.
So is it possible to load bitstream in parts, enough for basic PCIe endpoint within 100 ms to conform to PCIe spec and then load a bigger design afterwards?
I once had to work with a hardware team to debug a "boot issue" where we were right on the margin due to a two-phase boot process (boot initial bitstream, check journal in flash, load active bitstream) and didn't even realize going into the debugging that we were close to the margin.
It's nice to be doing plain-old software again...
Earlier quoted context omitted.
I don't think it's supported for Spartan-6 though.
So it's not possible to implement compliant PCIe interface together with some bigger block with this board?
The easier thing to do would be to delay enumeration.
Oh, nice! On the other hand, seeing this on HN now I feel really inadequate, having just finished the prototype of my miniPCIe Arduino clone last weekend... Really need to level up too! KiCad source of the PCIeDuino: https://github.com/moonpunchorg/pcieduino Pictures: http://imgur.com/a/XiJ12
Oh, nice! On the other hand, seeing this on HN now I feel really inadequate, having just finished the prototype of my miniPCIe Arduino clone last weekend... Really need to level up too! KiCad source of the PCIeDuino: https://github.com/moonpunchorg/pcieduino Pictures: http://imgur.com/a/XiJ12
Which ARM-board you are using in those pictures?
VAB-600: http://www.viaspringboard.com/ or http://www.viaembedded.com/en/boards/pico-itx/vab-600/
VAB-820: http://www.viaembedded.com/en/boards/pico-itx/vab-820/ (better software, Freescale SoC)
VAB-1000: http://www.viaembedded.com/en/boards/pico-itx/vab-1000/ (at the moment Android only)
I hope to try other vendors' ARM boards too, I've made a list a few weeks ago of those that have mini-PCIe connectors, so plenty to experiment with....
(disclaimer, I'm currently working at VIA)
http://polysome.io/ The manufacturer. What purpose is this useful for? Can someone elaborate?
The board could be repurposed for the lowRISC project. It is also suitable for use with embedded routers and laptops as a crypto coprocessor or HSM.
We are pairing the first batch of prototypes with the PCengines apu1d4 (w/coreboot) and will provide these reference platforms to developers.
To be considered for a unit you need to compile a bitstream of the OpenSPARC T1 for the LX150T variant of this board.
Email development@polysome.io for more details
Thanks for all your encouragement !
Just wait till you see what's coming.
Earlier quoted context omitted.
It should be mentioned that the '100T device pictured actually requires the full paid version of ISE. The free-as-in-beer ISE Webpack only supports up to the '75T. Thankfully Xilinx implemented compatible packages through the device family, so lower devices are a drop-in replacement (mostly). Maybe one day we'll have a Free toolchain, but FPGA tools are much closer to chip design tools than to compilers, and the spac…
Supposedly, a lot of key FPGA patents are set to expire Real Soon Now, or just did, or something along those lines. I'm holding out hope that we'll have a true Open Source FPGA environment sooner or later, but it sure is taking it's time... :-(
I only have a passing understanding of the FPGA world, but I thought that everything in that space in shrouded in trade secrets. Do patent claim descriptions really have enough detail to help you produce a working bitstream?