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Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

semiconductor.samsung.com

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Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#41

Post by adrian_b »

slashdev wrote: post #29
monocasa wrote: post #27

Earlier quoted context omitted.

Nope, thermodynamics is weird at small scales. Hot spots can absolutely reach 1400C if not designed not to. Sophie Wilson (initial architect of the ARM processor) has talked about how poorly designed silicon can reach point temperatures hotter than a nuclear reactor steady state.

That’s crazy. I thought maybe some of the other elements used in modern semiconductors might melt first. The wiring seems like a potential problem. But before that even the elements they use in the transistors themselves could be an issue.

Like I have already said in another comment, semiconductors and metals behave differently when temperature increases.

For metals the electrical resistance increases with temperature, causing a negative feedback that limits the increase of the temperature, while for semiconductors the electrical resistance decreases with temperature above a certain threshold, so once that threshold is reached positive feedback increases the temperature very quickly until the semiconductor is melted, unless there is some protection system that limits the power dissipation through the semiconductor.

That is why it is very easy to melt silicon in an integrated circuit or in a discrete device, despite its high melting point.

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#42

Post by adrian_b »

jamesik wrote: post #39
boznz wrote: post #26

Earlier quoted context omitted.

I take your point, but an IC is not pure silicon

Indeed. For instance, dopants can diffuse and metals can intermix with silicon (silicide formation), both degrade device performance. Solder and packages melt before any of this happens.

It is easy to melt the semiconductor in a semiconductor device long before the solder or package materials are melted.

Above a certain temperature threshold, the electrical resistance of semiconductors drops exponentially with temperature, which is why NTC (negative thermal coefficient) thermistors are made of semiconductor materials.

This causes a positive feedback loop that increases the current very quickly and concentrates it through a narrow channel through the semiconductor (so the current density can be extremely high even when the total current is still low), which can easily reach 1500 Celsius degrees, melting the silicon, while the temperature of the package and of the solder remains very low (because the time is too short for the temperature to propagate outwards from the melted silicon channel).

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#43

Post by blenklo »

amelius wrote: post #25
mschuster91 wrote: post #21

> By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint. The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.

A much greater achievement than training frontier models, or building any kind of software stack, if you ask me. Yet everybody seems to think the moat is with the AI companies or nvidia.

For sure but a weird comparision. These are completly different technologies.

I don't think a optics engineere can train a frontier model.

But also a frontier model requires a lot of compute.

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#44

Post by khurs »

zuzululu wrote: post #34

so whats the implication for average joes here ? have no idea what these technical terms mean....

Making chips smaller is very hard at the nanometer sizes, and it requires the kind of expert equipment made by one single Dutch company (ASML) and expertise only the likes of Taiwan's TSMC have.

Stacking means keeping the same size, but adding more of it so it matches the same compute power as the more advanced smaller chip designs.

China (who is banned from buying from ASML) is currently pursuing stacking as a short to medium term strategy until they can catch up to TSMC.

https://policy.economy.ac/news/2025/11/202511284344

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#45

Post by ksec »

amelius wrote: post #25
mschuster91 wrote: post #21

> By stacking multiple nanosheet channels, the effective channel width can be maintained even within a highly compact footprint. The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.

A much greater achievement than training frontier models, or building any kind of software stack, if you ask me. Yet everybody seems to think the moat is with the AI companies or nvidia.

And the money we are paying for it as consumer is ridiculously low. And yet all we have ever heard was they are being ripped off.

Generally speaking both HN and the internet rarely appreciate hardware advancement.

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#46

Post by saltcured »

marcosdumay wrote: post #36
saltcured wrote: post #17

Earlier quoted context omitted.

The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up? And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.

> The shorter connections could lead to faster rise times though, right? Not if you replace that length with more capacitors stacked on top of each other.

Hah, yeah.

I've been naively assuming they are now making high quality vias, so that circuit characteristics would be similar in either vertical or horizontal direction.

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#47

Post by zuzululu »

khurs wrote: post #44
zuzululu wrote: post #34

so whats the implication for average joes here ? have no idea what these technical terms mean....

Making chips smaller is very hard at the nanometer sizes, and it requires the kind of expert equipment made by one single Dutch company (ASML) and expertise only the likes of Taiwan's TSMC have. Stacking means keeping the same size, but adding more of it so it matches the same compute power as the more advanced smaller chip designs. China (who is banned from buying from ASML) is currently pursuing stacking as a short…

excellent answer thank you that makes a lot of sense are there any downsides to that ? more heat ?

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#48

Post by slashdev »

adrian_b wrote: post #41
slashdev wrote: post #29

Earlier quoted context omitted.

That’s crazy. I thought maybe some of the other elements used in modern semiconductors might melt first. The wiring seems like a potential problem. But before that even the elements they use in the transistors themselves could be an issue.

Like I have already said in another comment, semiconductors and metals behave differently when temperature increases. For metals the electrical resistance increases with temperature, causing a negative feedback that limits the increase of the temperature, while for semiconductors the electrical resistance decreases with temperature above a certain threshold, so once that threshold is reached positive feedback increas…

Very surprising! Thanks for sharing

Re: Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

#49

Post by flossEveryday »

adrian_b wrote: post #40
slashdev wrote: post #23

Earlier quoted context omitted.

Pure silicon melts at 1400 C You must be thinking of something else

The melting of silicon was a common phenomenon already during the second breakdown of power transistors, e.g. in audio amplifiers or in TV sets, more than a half of century ago. In semiconductors there is a positive feedback between temperature and the current that passes through them, so once a certain threshold is passed, the current and the temperature grow very quickly until the semiconductor is melted. This is o…

wow, i had heard of transistor thermal runaway, but i didn't know you could reach silicon melting point temperatures. though i guess in hindsight it makes sense that, considering that during the manufacturing process semiconductors are already exposed to very high temperatures, if you are instantly permanently altering a device with heat (as you do when you destroy it through thermal runaway), you must be reaching comparably high temperatures.

what type of people look at heat transfer at the device level in an IC (and at such short time scales)? where can i learn more about that? this looks like it could have an impact in analog power circuits, because even if you don't destroy the transistor you could alter its characteristics, but i haven't seen a lot of attention being paid to that. personally i guess i figured individual transistors never went significantly beyond the temperature ranges we already consider for the circuit as a whole.

thank you for sharing

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