Earlier quoted context omitted.
Another major difference is the memory model. In X86 other CPU’s must always see the writes of a core exactly in the right order. This limits the ability to reorder store ops significantly. ARM requires a memory barrier for this. This is a major reason why X86 emulation is so slow. One must basically issue a memory barrier after every store op. M1 actually also implements the X86 memory model too in HW. It’s only usa…
I am trying to wrap my head around whether ARM's looser memory model is a fundamental performance advantage or not. I had always assumed that the looser memory model must have a performance benefit. But this comment from last week argues that it doesn't really buy that much, and that a bigger buffer can eliminate most of the difference: https://news.ycombinator.com/item?id=25263461 If TSO forces flushing of store buf…
Without that the store buffers can be kept unflushed to, as an example, see if one can get a full cacheline or whatnot and only flush then.
The comment is correct that an X86 with heavy reordering backend will beat arm without one. However arm with one does handily beat X86 with one. Case in point: M1