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For those interested, there is a master thesis from the '90 that discussed a prototype reversible ISA + RTL that wasted (in theory) no power for the logic (non-IO) parts [2].
[1] http://en.wikipedia.org/wiki/Reversible_computing [2] http://dspace.mit.edu/bitstream/handle/1721.1/36039/33342527...
I hoped the article had a look at which parts of those ISAs were reversible, and thus did not dissipate energy. For those interested, there is a master thesis from the '90 that discussed a prototype reversible ISA + RTL that wasted (in theory) no power for the logic (non-IO) parts [2]. [1] http://en.wikipedia.org/wiki/Reversible_computing [2] http://dspace.mit.edu/bitstream/handle/1721.1/36039/33342527...
Earlier quoted context omitted.
Normalization is nice for a mental exercise, but I cannot buy a normalized phone with a normalized i7 that fits in my normalized pocket. Engineering is the art of trade-offs and the i7 has traded off size and power to achieve speed. That is great when you have an i7-scale size and power budget, but if the i7 exceeds your power or size budget it is a non-starter regardless of how efficient (when normalized) it is. Ful…
There are x86 phones on the market that have similar weight/shape/battery life to ARM phones. Anandtech reviewed one two years ago and found it in the middle of the pack with respect to energy. The question for Intel is dialing down the profit knob: how much of a hit do they want to take on each unit shipped, by competing with ARM for tiny phone chips.
With ARM different companies can license the design and include different system components on the chip. With Intel you need to take a packaged chip provided by Intel. This can allow a system power and cost advantage compared to having multiple chips. It is however a licensing/business model issue rather than a fundamental ISA issue.
ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it…
So the MIPS ISA is considered to be 'pure' RISC? My rule of thumb: if something is conceptually "pure" instead of a complicated, carefully balanced mix of grey, its usually not worth considering. I found this to be true for programming languages, ISAs, politics etc. It is interesting how purity has a very strong allure - maybe our brains are naturally drawn to a reduced state of complexity, and thus energy consumptio…
Or maybe complicated more often than not is just not a "carefully balanced mix of grey" but more of a clusterfuck .. and we learned to be wary of it.
Have a look at this: http://www.infoq.com/presentations/Simple-Made-Easy
Earlier quoted context omitted.
So the MIPS ISA is considered to be 'pure' RISC? My rule of thumb: if something is conceptually "pure" instead of a complicated, carefully balanced mix of grey, its usually not worth considering. I found this to be true for programming languages, ISAs, politics etc. It is interesting how purity has a very strong allure - maybe our brains are naturally drawn to a reduced state of complexity, and thus energy consumptio…
> It is interesting how purity has a very strong allure - maybe our brains are naturally drawn to a reduced state of complexity, and thus energy consumption? Or maybe complicated more often than not is just not a "carefully balanced mix of grey" but more of a clusterfuck .. and we learned to be wary of it. Have a look at this: http://www.infoq.com/presentations/Simple-Made-Easy
If elegance and simplicity are achievable without making too many sacrifices, great! I'd choose Clojure over C++ any day.
Earlier quoted context omitted.
The Loongson is a 90nm part, the others are 32-45nm. No ISA is going to make up for a doubled transistor size. Really the notable thing to me isn't the ISA nonsense at all. It's how singular a success the Cortex A9 core is. It came at exactly the right moment in history and hit exactly the right sweet spot, being significantly beefier than the A8 yet only minimally more power-hungry. Krait has followed on pretty well…
Yeah, based on just the data in this article, I would see A9 as preferable to A15 for using as the CPU of a mobile device.
ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it…
The Loongson is a 90nm part, the others are 32-45nm. No ISA is going to make up for a doubled transistor size. Really the notable thing to me isn't the ISA nonsense at all. It's how singular a success the Cortex A9 core is. It came at exactly the right moment in history and hit exactly the right sweet spot, being significantly beefier than the A8 yet only minimally more power-hungry. Krait has followed on pretty well…
It would be interesting to see how the A7 also compares to the A8/A9, since it's supposed to be a more power-efficient version of the A15.
"The ISA being RISC or CISC seems irrelevant.". I thought these were all RISC processors when you get past the instruction decoder.
Which still leaves the question of the cost of the instruction decoder.
ARM and x86 are rather close, but the real disappointment here is the MIPS Loongson, which is basically the "original RISC ISA". Unfortunately I've encountered a huge number of people, particularly academics, who still think (and teach) that MIPS or minor variants of it are the "best" ISAs and that one can easily make cheap, fast, and power-efficient processors based on it. Looking at the current state of things, it…