Intel Reveals Post-8th Gen. Core Architecture 10nm+ Ice Lake

Post by gruez » Wed, Aug 16, 2017, 12:52 PM UTC

hvidgaard wrote: post #80

slededit wrote: post #62

Earlier quoted context omitted.

Primecoin is a good example. If you look at the implementation it requires generating a tightly packed bitfield for the sieve and then randomly accessing it after. Lots of synchronization required so you don't overwrite previously set bits are required and the memory accesses are random so its suboptimal for the GPU's memory subsystem. It took under a year for a GPU miner to come out. Having optimized it for Intel in…

> a thousand cores can brute force its way through anything This is so fundamentally wrong that your complete lack of understanding the underlying math is obvious. Let us use 1024bit RSA as the key to bruteforce. If we use the entire universe as a computer, i.e. every single atom in the observable universe enumerate 1 possibility every millisecond, it would take ~6 * 10^211 years to go through them all. In comparison…

Post by baybal2 » Wed, Aug 16, 2017, 1:03 PM UTC

zerohp wrote: post #64

ktRolster wrote: post #59

Earlier quoted context omitted.

At some point, maybe we'll start seeing RAM put onto the CPU itself. I mean, more than it already is (with cache).

You will see stacked memory and silicon interposers, but you won't see main memory on the CPU die. DRAM is based on an array of what is called "trench capacitors." The fabrication process is sufficiently different that they don't even make these in the same facility, much less on the same die process. An array of trench capacitors will always be smaller than transistor based memory (SRAM.)

Post by gsnedders » Wed, Aug 16, 2017, 1:12 PM UTC

deepnotderp wrote: post #45

jacquesm wrote: post #13

Earlier quoted context omitted.

The step from 14 to 10 nm is huge . Both from a technological perspective on the manufacturing side as well as on the effect it will have to the number of transistors on a die and the power consumption of those transistors. Remember that power consumption and the number of transistors are related to the surface area so there is a square factor in there. 14 nm ^2 = 196, 10 nm ^2 = 100, so that's almost a doubling of t…

Yeah, so the node names now apparently refer to the "smallest feature size", which is some random thing on the M0 metal layer. Source - from a former Intel engineer for more than a decade

Post by justin66 » Wed, Aug 16, 2017, 1:22 PM UTC

thinkfurther wrote: post #117

piva00 wrote: post #87

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You know the depth of how unrealistic is your advice, right?

Do you know the depths of not taking that advice and what lurks in them? Do you know that if everybody simply took it to heart, there'd be nothing unrealistic about it at all? How many months of abstinence and solidarity would be required to end these practices, or the companies if they so wish? And then that money simply shifts to ethical companies and we actually have a future. Or, we keep pretending it's all so ve…

Post by noir_lord » Wed, Aug 16, 2017, 1:46 PM UTC

dr_zoidberg wrote: post #178

Boothroid wrote: post #128

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Memory and storage. Still big gains to be had there. Imagine if your whole hard drive was RAM speed. Also more specialised cores e.g. DSP, and customisable hardware i.e. FPGA.

I distinctly remember a benchmark (which my google-fu is currently unable to find) between Intel chips with and without the Iris chip. On similar conditions (clock base/turbo and core count), the Iris chip had about a 20% performance advantage. It wasn't explained in the benchmark, but the only reason I could imagine was the Iris chip worked as an L4 cache because the benchmark was not doing graphics stuff. That is w…