Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake' • Hacker News Board

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#31

Post by solomatov » Mon, Jul 06, 2015, 4:48 PM UTC

AnonNo15 wrote: post #27

solomatov wrote: post #17

Earlier quoted context omitted.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

3D stacking. Heat dissipation is the limitation in this case, not the process size.

3D stacking won't solve heat dissipation problem, it will only worsen it. If we add N layers, we will increase heat in N times.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#32

Post by trynumber9 » Mon, Jul 06, 2015, 4:51 PM UTC

bryanlarsen wrote: post #23

agumonkey wrote: post #19

Earlier quoted context omitted.

The GPU takes resources and put pressure on the design, at the expense of CPU logic. I think what he meant to say is that an intel CPU-only could devote more transistor to logic without having to deal with so much heat which might still be a problem at 10nm.

I'd argue the converse: when you are benchmarking a CPU intensive application, the GPU is mostly idle and not generating much heat, giving you margin to push the CPU transistors harder. GPU designs are also much more regular than CPU designs, so heat is spread much more regularly rather than in a few hot spots. The regularity also makes it easier to transition to a new node.

Intel doesn't have a problem dissipating heat from their all-CPU Xeon giants. It stands to reason that without the GPU they could either make wider or more cores while staying in the 80-90W TDP.

Most of the die space would end up going to larger caches, which are also very regular.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#33

Post by duaneb » Mon, Jul 06, 2015, 4:58 PM UTC

agumonkey wrote: post #19

bryanlarsen wrote: post #10

Earlier quoted context omitted.

That may explain why Broadwell isn't significantly faster than Sandy Bridge, but I don't understand how it has anything to do with this announcement. How does 10nm being delayed 1 year have anything to do with integrating graphics?

The GPU takes resources and put pressure on the design, at the expense of CPU logic. I think what he meant to say is that an intel CPU-only could devote more transistor to logic without having to deal with so much heat which might still be a problem at 10nm.

I was under the impression that heat per transistor is inversely proportional to the size of the die. So it makes sense that reducing the size would be, primarily, a heat problem. The GPU adds much, much, much more logic to the CPU, making heat constraints more difficult to deal with.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#34

Post by [deleted] » Mon, Jul 06, 2015, 4:59 PM UTC

bryanlarsen wrote: post #12

solomatov wrote: post #9

It seems that we almost reached the limit of Moore's law. 5nm seems to be a physical limit at least for sustainable changes of current technologies.

Reference "The Boy who cried Wolf". That pronouncement has been made and proven wrong way too many times for anybody to take it seriously. Eventually the wolf will come and the limit will be reached, but until it happens nobody will believe it.

[deleted]

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#35

Post by duaneb » Mon, Jul 06, 2015, 5:00 PM UTC

solomatov wrote: post #17

bryanlarsen wrote: post #12

Earlier quoted context omitted.

Reference "The Boy who cried Wolf". That pronouncement has been made and proven wrong way too many times for anybody to take it seriously. Eventually the wolf will come and the limit will be reached, but until it happens nobody will believe it.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

> But how is this is possible?

That's the question to answer. It's just as hard to prove that you CAN'T assemble a transistor of that size.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#36

Post by agumonkey » Mon, Jul 06, 2015, 5:14 PM UTC

duaneb wrote: post #33

agumonkey wrote: post #19

Earlier quoted context omitted.

The GPU takes resources and put pressure on the design, at the expense of CPU logic. I think what he meant to say is that an intel CPU-only could devote more transistor to logic without having to deal with so much heat which might still be a problem at 10nm.

I was under the impression that heat per transistor is inversely proportional to the size of the die. So it makes sense that reducing the size would be, primarily, a heat problem. The GPU adds much, much, much more logic to the CPU, making heat constraints more difficult to deal with.

Good point, higher density but also lower voltage, I don't know how these balance each other.

http://imgur.com/PD14VtN shows how large GPUs can be. As other said, GPU might spend a lot of time in low workload I don't know. And I don't know if have 30% more transistor budget could help heat generation and dissipation...

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#37

Post by marcosdumay » Mon, Jul 06, 2015, 5:24 PM UTC

ZenoArrow wrote: post #26

solomatov wrote: post #17

Earlier quoted context omitted.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

It'll be interesting to see the parts that silicon photonics and molecular assembly come to play in meeting the future process nodes. I agree with those who say we'll reach a cost barrier before we reach a technical barrier. If I were to make a wild guess, I'd say 7nm will be that limit, and that it'll be about 5 years away (Moore's Law is already broken and isn't likely to be fixed any time soon, hence the slower ti…

A cost barrier is the most common manifestation of a technical barrier.

There's no way silicon microlitography will keep working once transistors are just a few atoms big. In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#38

Post by cma » Mon, Jul 06, 2015, 5:28 PM UTC

bryanlarsen wrote: post #23

agumonkey wrote: post #19

Earlier quoted context omitted.

The GPU takes resources and put pressure on the design, at the expense of CPU logic. I think what he meant to say is that an intel CPU-only could devote more transistor to logic without having to deal with so much heat which might still be a problem at 10nm.

I'd argue the converse: when you are benchmarking a CPU intensive application, the GPU is mostly idle and not generating much heat, giving you margin to push the CPU transistors harder. GPU designs are also much more regular than CPU designs, so heat is spread much more regularly rather than in a few hot spots. The regularity also makes it easier to transition to a new node.

giving you margin to push the CPU transistors harder

If you dedicated the GPU space on the core to more CPUs, you could cycle your workload amongst more cores, even if you made it so that only the same number were active at any given instant.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#39

Post by JaRail » Mon, Jul 06, 2015, 6:04 PM UTC

solomatov wrote: post #18

pavlov wrote: post #15

Earlier quoted context omitted.

That's mainly a GPU problem though.

Now GPU is part of CPU, at least in Intel processors.

Yup. You notice a huge difference in smoothness when switching a high-end MBP between integrated and dedicated graphics.

Re: Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby Lake'

#40

Post by duaneb » Mon, Jul 06, 2015, 6:10 PM UTC

agumonkey wrote: post #36

duaneb wrote: post #33

Earlier quoted context omitted.

I was under the impression that heat per transistor is inversely proportional to the size of the die. So it makes sense that reducing the size would be, primarily, a heat problem. The GPU adds much, much, much more logic to the CPU, making heat constraints more difficult to deal with.

Good point, higher density but also lower voltage, I don't know how these balance each other. http://imgur.com/PD14VtN shows how large GPUs can be. As other said, GPU might spend a lot of time in low workload I don't know. And I don't know if have 30% more transistor budget could help heat generation and dissipation...

I think there are two constraints the GPU would impose on the CPU:

1. Static resource contention—i.e. how many transistors are allocated to a task.

2. Power/Heat contention: assumably the CPU can run at full force without the GPU. When the GPU is also cranking, it's unclear how the processor divvies up the power. Optimally, it would not affect the other, but with so much money going into power management and conservation research vis-a-vis phones, it wouldn't shock me to find that it cut into the CPU significantly: I would suspect the GPU is a much more recognizable piece of quality hardware to most consumers. My Moto E is an impressive, cheap piece of hardware, but still chokes hard on lollipop animations.