Here's a good book guiding through an implementation of a simple 8 bit processor (based on 8080 architecture) with VHDL:
http://www.amazon.com/Design-Computers-Complex-Digital-Devic...
The same author also wrote another book later where he shows a design of ARM like 16 bit CPU with pipelining.
Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
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Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#12Earlier quoted context omitted.
+1 for Verilog. SystemVerilog is the way to go.
I like VHDL. Verilog and non-blocking vs blocking assignments can trip you up so easily. As for verbose code, you spend way more time debugging and thinking about how to structure a program than you do writing text on the screen.
I prefer Verilog but what you say is true or at least should be true if you want to end up with a good, easily debuggable result.
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#13For those interested in other FPGA boards, Digilent makes a whole series of affordable ones.
https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,4...
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#14For those interested in other FPGA boards, Digilent makes a whole series of affordable ones. https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,4...
As an alternative, this is the one I've been using: http://numato.com/mimas-v2-spartan-6-fpga-development-board-...
It's pretty cheap, but it has a whole bunch of nice things built onto it, and a simple flasher script that actually works on Linux!
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#15Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.
+1 for Verilog. SystemVerilog is the way to go.
I like VHDL, but SystemVerilog does have some very nice features.
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#16For those interested in other FPGA boards, Digilent makes a whole series of affordable ones. https://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,4...
I can recommend the boards from TerAsic. Solid design and
Readable documentation. Altera ships boards
from TerAsic for their courses. Good value
for money.
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#17>bonus points goes to the people who realise there is an odd thing about the form of the baz (branch if Ra is zero) instruction. Is this because the second argument is another register (presumably containing an address to branch to) instead of a label?
Just before the loop there is this instruction, "load.l r7, $mul16_fin".
Prehaps this is so the assembler/linker/loader doesn't need to resolve what address the label ends up having
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#18My best advice: synthesize early and often, and spend the time to poke around in the synthesis schematic viewer - Webpack still includes this I believe. It's a great way to compare what you wrote in code to the logic you intended to implement in your mind's eye (or better yet, your notebook).
And read the design guidelines from the FPGA vendor
of the device you are targeting. Xilinx,
Altera (Intel), Microsemi and Cypress all
have different rules for mapping things like
memories, write enables etc.
Xilinx is happy to not reset registers, Altera will generate a bigger design if reset is not stated in the code.
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#19And this is what you can use if you want to implement an instruction or two in Verilog without having to implement the rest of the CPU. Plus a flexible compiler toolchain: https://github.com/combinatorylogic/soc
(never mind it being multicycle, it was done this way for a reason, and dropping in a RISC design should be fairly trivial.)
Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
#20Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.
Verilog is C to VHDL's Pascal, maybe. Better but really not that much different. Check out the RISC-V folks' work in Chisel (a Scala-based DSL) for some great examples of what HDL code should be like.
It's not perfect either, but reading it is vastly more pleasant than plodding through a design in one of the Vs.