Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#1

Post by luu » Fri, Jun 19, 2015, 12:06 AM UTC

Designing a CPU in VHDL, Part 1: Rationale, Tools, Method
labs.domipheus.com

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#2

Post by bobp127001 » Fri, Jun 19, 2015, 1:10 AM UTC

>bonus points goes to the people who realise there is an odd thing about the form of the baz (branch if Ra is zero) instruction.

Is this because the second argument is another register (presumably containing an address to branch to) instead of a label?

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#3

Post by alain94040 » Fri, Jun 19, 2015, 1:18 AM UTC

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason.

Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#4

Post by p1esk » Fri, Jun 19, 2015, 1:48 AM UTC

alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

+1 for Verilog. SystemVerilog is the way to go.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#5

Post by krapht » Fri, Jun 19, 2015, 1:52 AM UTC

p1esk wrote: post #4

alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

+1 for Verilog. SystemVerilog is the way to go.

I like VHDL. Verilog and non-blocking vs blocking assignments can trip you up so easily. As for verbose code, you spend way more time debugging and thinking about how to structure a program than you do writing text on the screen.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#6

Post by cyanoacry » Fri, Jun 19, 2015, 2:13 AM UTC

alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

Having programmed in both, I prefer VHDL--the two take different paths, analogous to functional vs imperative programming.

The type checking that makes VHDL so annoying is also the same type checking that's saved me. Coming from Haskell, VHDL was a much easier language to learn than Verilog.

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#7

Post by jevinskie » Fri, Jun 19, 2015, 2:14 AM UTC

alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

Yikes, I find Verilog to be much too C like while VHDL is almost Python like. I enjoy the strictness. VHDL 2008 (should be supported by tools now) fixes a lot of VHDL's warts. Also, I love the two process design methodology that you can use with VHDL. It lets you single-step through your VHDL code in the simulator as if it were plain procedural code!

http://www.gaisler.com/doc/vhdl2proc.pdf

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#8

Post by [deleted] » Fri, Jun 19, 2015, 2:14 AM UTC

alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

[deleted]

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#9

Post by bisrig » Fri, Jun 19, 2015, 2:19 AM UTC

My best advice: synthesize early and often, and spend the time to poke around in the synthesis schematic viewer - Webpack still includes this I believe. It's a great way to compare what you wrote in code to the logic you intended to implement in your mind's eye (or better yet, your notebook).

Re: Designing a CPU in VHDL, Part 1: Rationale, Tools, Method

#10

Post by bisrig » Fri, Jun 19, 2015, 2:26 AM UTC

alain94040 wrote: post #3

Please do yourself a favor and use Verilog instead. I understand that VHDL forces you to write cleaner code, but it's also frustrating for no good reason. Also, start looking into pipelining ASAP. Implement one micro-arch, benchmark it, then try to do better. It's a great way to learn.

I will never forgive the Verilog powers that be for allowing the 'reg' keyword to describe "things that are not registers". But joking aside, the differences between VHDL and Verilog are minor in this context. And one person's frustration is another's saving grace due to strictness etc.