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The Lack of Open Tooling for FPGAs

curtis.io

61–70 of 125 posts

Re: The Lack of Open Tooling for FPGAs

#61

I'll offer a guess as to why the FPGA manufacturers are hostile to open tools. Open tools reveal the internal details of their FPGA hardware which is their bread and butter. I think it is probably the wrong approach, but that sort of thinking is common around intellectual "property."

That's basically the same reasoning used by most GPU manufacturers, but two of the biggest players in that market have chosen not to act that way and don't seem to be suffering at all for it.

Re: The Lack of Open Tooling for FPGAs

#62

Having done my graduate studies in FPGA architecture and software, I can definitely see where the author is coming from. In fact, it seems like the entire hardware development industry has to face the issue of most tools being closed-source. Although I don’t have a solution for the technology specific phases (Place and Route, Bit Stream Generation, etc.), I am actually part of a company that is trying to help solve t…

Do you have an offering that would allow me to code up a SystemVerilog->Verilog translation script on a hobbyist budget? I'm stuck coding for my SP605 in Verilog (or VHDL) but I would really like to be able to use structs and interfaces from SystemVerilog. Coming from software dev it's insane: The $500 devkit doesn't support structs and I would have to pay $1300 to get one that does. Meanwhile C has had structs for 4…

I've had similar needs but couldn't find an existing tool, nor a parser on which to build. There are some open source parsers [0], but they don't seem to do preprocessing and hence lose a lot of context.

So I made a parser that might work for your use-case given some work:

https://github.com/svstuff/systemverilog

It works for some fairly big codebases, so I know it's not completely broken. I'm not very proud of the scala code, it's quite ugly in places. But at least there are some tests :p

[0]: this also seems active worth checking out: https://github.com/gburdell/parser

EDIT: added link to other parser.

Re: The Lack of Open Tooling for FPGAs

#63

Thinking about this topic some more, it seems hard to gain the critical-mass of contributors for such an open-source tool. Place-and-route for example, requires a very specific set of knowledge in both optimization (comp-sci), and hardware (electrical). Most of the people who have these skill sets are probably already employed by the major FPGA vendors and under NDA to not contribute to such an open-source tool. I've…

OP here

This is a severe problem that saddens me greatly. For now I am just writing tools to make JTAG/SPI/etc loading of chips Ubiquitous to the developer writing software/netlists for them. I do not know enough about the place and route math and routines, nor have I seen enough details of real life chips to know the types of real challenges faced. But I will cross that bridge when I get there (maybe it will be someone else :)).

I personally have a huge issue letting anything fundamental I figure out be marked down as the property of a company to have and hold for 20+ years. But I understand the financial rewards and interesting problems are more than enough for many people, so I can not hold it against a student with a PHD worth of debt to need cash. Sigh.

Hopefully if a good enough extensible base exists, people will add pieces on (whatever they can get away with) over a long time. That is all I can really hope for.

Re: The Lack of Open Tooling for FPGAs

#64
I've been wondering recently how viable it would be to implement an FPGA-within-an-FPGA:

  * Create a model of a simple, open FPGA.
  * Create tools to support the open FPGA.
  * Synthesize the FPGA for an existing proprietary FPGA.
  * Install bitstream in SPI NOR.
  * Ignore the proprietary FPGA from now on - work with the open FPGA that's inside it.
Yes, it would be absurdly inefficient. However, you can buy pretty huge FPGAs for very little these days. If the ratio of host:target LUTs isn't too bad, and you can find constructs which synthesize efficiently, it might yield something usable.

Perhaps it could be a way of bootstrapping an "open" FPGA effort.

Re: The Lack of Open Tooling for FPGAs

#65
post #42

Earlier quoted context omitted.

OP here You are right that my particular project is not the biggest piece, but it is the part that pisses me off. I can deal with Xilinx's crappy compiler if I can program my chips with ease..... or maybe I should say UNTIL I can program my chips with ease. Then my focus will change hehe. Icarus works but it has been maintained by one 'eccentric' guy for quite a while and the code base is semi unapproachable. I belie…

I fully support the spirit of what you're doing btw. I hope you don't take my comments as somehow dumping on your work ;). What is "crappy" about Xilinx tools aside from the UI? I'm genuinely curious. I don't think the comparison between synthesis tools and compilers hold. They are different beasts. I think compiler equivalent is sim tools which should be open and free. Everyone that I've talked to who uses Keil uses…

Xilinx iMPACT (the FPGA programmer) bugs:

On one version, it can load the project it saved, but then crashes when you go to program. So you have to scan and reload all the data files every time you start it.

Later version, failed to program the chip at the last stage of the process. Diagnosed that over phone tag where the user was non-technical and on a machine not connected to the Internet. Exact same chip as above.

Another later version has different iMPACT bugs than that first version above, but right now I haven't been able to get it to work on any Win 8.1 machine so I don't remember which bugs it has.

Re: The Lack of Open Tooling for FPGAs

#66
post #33

Earlier quoted context omitted.

I can't speak for OP, but my interest is in signal processing. DSP and FPGAs are a great match and with the boom in software defined radio, having reconfigurable DSP capabilities is extremely useful. For example, if 802.11b devices had been built using FPGAs, an upgrade to 802.11g could have been an OTA update. Or a new Bluetooth variant emerges (e.g. BLE) and support could be added to computers and phones overnight.…

SDR uses orders of magnitude more power than an ASIC implementation which is why no one uses them except for base stations -- such as cell towers. FPGA based design for crypto would have the same timing attack as CPU. It can be worked around the same way it would for a CPU.

Sure, ASICs are always going to beat FPGAs and CPUs in power consumption for the same task, but there are also applications where the ability to update the system far outweigh the power requirements.

Interestingly, SDR is being used for the UK's small scale digital radio station trials this year. Off the shelf SDR hardware appears to be performing well enough at a lower cost than bespoke DAB hardware. Again, this fits in with your base station category.

You're right about timing attacks, I have no idea what I was thinking there. Would they be better for power analysis attacks? I guess if we're concerned about that then we'll end up back at ASICs again.

Re: The Lack of Open Tooling for FPGAs

#67

Earlier quoted context omitted.

Do you have an offering that would allow me to code up a SystemVerilog->Verilog translation script on a hobbyist budget? I'm stuck coding for my SP605 in Verilog (or VHDL) but I would really like to be able to use structs and interfaces from SystemVerilog. Coming from software dev it's insane: The $500 devkit doesn't support structs and I would have to pay $1300 to get one that does. Meanwhile C has had structs for 4…

How about using VHDL and records? I think these are synthesizeable outside of ports. VHDL is a much better language from a software engineering standpoint than Verilog.

I know nothing about VHDL -- I vaguely remember hearing someone say it suffered from the same issue so I didn't pursue it. Thanks for the tip!

Re: The Lack of Open Tooling for FPGAs

#68

First, just wanted to say that I find this topic really interesting. I'm trying to understand who the target user is for open-source FPGA tools. For many hardware companies, the risk of using an unproven tool is too severe. Unlike software, you can't just push out a patch if there is a bug. I mean, in theory, I guess you can since FPGAs are reconfigurable, but it is probably not very straightforward from a deployment…

OP here

I get there is a big difference between hardware and software, but I feel that certain parts of the gaps are closing. They will not CLOSE, but as they get closer we can learn from each other.

With that said, to address your point: Linux is one of the most dominant systems for servers. Google, Facebook, Twitter, etc use it for almost all of their backend systems. They use it not just because it is free but because it is proven and scalable. Open source databases and web servers also enjoy considerable (sometimes dominant) share. There are companies that provide support contracts for Linux (Suse, Redhat) and that model has worked to fund other open software.

So I think that establishes that a company will use open software.

As for being scary, you are correct that is a primary decision making motivation. It is why many professionals in tons of industries still run windows XP. Often they NEED XP because the software they rely on is so dependent on that specific ecosystem that huge rewrites are necessary in order for it to work on anything else, and this work (even if done by the original distributor) will take years for the tools to be stable again. This is not good engineering on the part of the tool designers. The crippling fear of NEVER TOUCHING ANYTHING is something that the open software alternatives seem to be alleviating in corporate environments since the late 90s.

The lifecycles of putting a phone together is much faster than Intel designing a processor, or Xilinx designing a new FPGA. building boards in phones and laptops is a complex game of Lego and placing them around so the timing diagrams work in all expected use cases. And if the timing does not work in some cases, whatever, people get a phone a year. Hell on my Galaxy S3 Verizon said 'oh yeah that is a known issue where sometimes the GPS just does not work because of loose wires, that was fixed in the S4, I think, which is only $$$.'

You are also correct about direct support from the company. In face make Xilinx enough money and they will share their secrets with you. But I am more targeting small to medium development. If open tools become popular and stable enough to get market share in hobbyist up to medium sized companies, it will only be so many years before bigger companies hire new engineers who grew up using open tools and have no patience for tools that have to be emulated in windows XP and have 35 nested sub menus for enabling a feature.

I do not feel attacked at all. You brought up interesting points. I hope i did them justice and did not ramble since there were a lot of points to hit.

Re: The Lack of Open Tooling for FPGAs

#69
post #64

I've been wondering recently how viable it would be to implement an FPGA-within-an-FPGA: * Create a model of a simple, open FPGA. * Create tools to support the open FPGA. * Synthesize the FPGA for an existing proprietary FPGA. * Install bitstream in SPI NOR. * Ignore the proprietary FPGA from now on - work with the open FPGA that's inside it. Yes, it would be absurdly inefficient. However, you can buy pretty huge FPG…

Amusingly the Xilinx license states that you are not allowed to use the bitstreams generated by their software in any device that they did not manufacture. This means if you implemented a xilinx fpga in an altera fpga, it would be against the agreement to program the inner xilinx fpga with the bitstream. The more you know!

Re: The Lack of Open Tooling for FPGAs

#70

This does a good job of capturing the first part of the problem. Note that Xilinx did make an "open" FPGA part, the 3000 series, it did not do well for them. The critical thing to understand, is that FPGA users (the big ones, not the casual ones) don't want them to be open. They want the information they program into them to be secret so that their hardware is not easily duplicated by the folks in China and mass prod…

If there's so much value there, how are these companies stopping internal espionage? If a company wanted to see what their competitors were doing to gain a large advantage, they could certainly field a candidate to work as an agent for their competitor. It sounds like how Nikon doesn't document the NEF format and pretends their binaries are the only way to decode such files. Except obviously the secrets these hardware companies have is far more than a simple RAW format.
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