Related project : https://github.com/m-labs/migen
Migen is quite different from MyHDL. Migen folks specifically wrote about differences from MyHDL here:
MyHDL – Design hardware with Python – Examples
21–30 of 33 posts
Re: MyHDL – Design hardware with Python – Examples
#22I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly): lt : BoolO…
I worked on creating a HDL as a DSL in Haskell as my undergraduate project: https://github.com/aninhumer/mantle
I haven't touched the code since I graduated last year, and I've had various ideas about how I should restructure it since then. The most interesting part of the project is probably the implementation of guarded channels, which turned out to admit useful Functor and Applicative instances.
I hope to start as a PhD student next year working on a new version of the language taking into account what I've learned since then. Most notably, GHC's recursive do-notation sounds like it will be incredibly useful for creating the kind of monadic cyclic graph structures needed for hardware.
Re: MyHDL – Design hardware with Python – Examples
#23Earlier quoted context omitted.
I think this is where FPGAs might prove very useful. Even if the designs made on FPGAs are small-scale, amateurish or sub-optimal today, they will help develop an ecosystem of tools, including open-source tools, that will ultimately help larger-scale open-source hardware.
The problem with FPGAs is the design software. Have you ever tried to use WebPACK ISE or Quartus? Both of them blow. Terrible UI, terrible design, terrible licensing requirements. We need simple, easy, powerful, and free tools for FPGA development before open source FPGA cores take off.
I agree. they do have command line tools, just look at the logs, and build your makefiles.
Re: MyHDL – Design hardware with Python – Examples
#24There is so much potential in open source hardware design. Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware. Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source soft…
> Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. That's pretty much what we did have, before RMS started GCC. I guess we need an RMS for hardware!
As a reminder, Stallmans's first attempt at GCC used the Pastel compiler source code from LLNL. http://gcc.gnu.org/wiki/History
> Hoping to avoid the need to write the whole compiler myself, I obtained the source code for the Pastel compiler, which was a multi-platform compiler developed at Lawrence Livermore Lab. It supported, and was written in, an extended version of Pascal, designed to be a system-programming language. I added a C front end, and began porting it to the Motorola 68000 computer.
I presume that the Pastel compiler therefore didn't require "hundreds of pages ..." in order to use and redistribute it. Or if it did, it wasn't binding on those who acquired the source.
Re: MyHDL – Design hardware with Python – Examples
#25I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly): lt : BoolO…
I worked on creating a HDL as a DSL in Haskell as my undergraduate project: https://github.com/aninhumer/mantle I haven't touched the code since I graduated last year, and I've had various ideas about how I should restructure it since then. The most interesting part of the project is probably the implementation of guarded channels, which turned out to admit useful Functor and Applicative instances. I hope to start as…
It looks interesting. Thanks for pointing it out to me.
Re: MyHDL – Design hardware with Python – Examples
#26Earlier quoted context omitted.
> Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. That's pretty much what we did have, before RMS started GCC. I guess we need an RMS for hardware!
As a reminder, Stallmans's first attempt at GCC used the Pastel compiler source code from LLNL. http://gcc.gnu.org/wiki/History > Hoping to avoid the need to write the whole compiler myself, I obtained the source code for the Pastel compiler, which was a multi-platform compiler developed at Lawrence Livermore Lab. It supported, and was written in, an extended version of Pascal, designed to be a system-programming lan…
True, but it only did Pascal, so I'll stand by my "pretty much" ;-)
Re: MyHDL – Design hardware with Python – Examples
#27Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
SystemC is the C++ equivalent that's been around for a long time. For a project I was working on, I used SystemC just for system-level modelling, it didn't bother me that I couldn't synthesize. To achieve decent clock-rates it would have been a good idea to reimplement the whole thing in "native" Verilog anyway (though my project didn't get that far). What SystemC provided me with is a way to sanity-check my model at…
MyHDL is implemented as a minimalistic pure Python library, which basically means that you can use Python features for modeling - pretty powerful. In addition, it supports conversion of a language subset, so that you can also use it as a synthesizable RTL language. The latter feature is absent from SystemC.
Re: MyHDL – Design hardware with Python – Examples
#28I don't know, i've been working with VHDL for 5 years and i don't see how this could be useful.
Usually we first develop our algorithms using fixed point math at Matlab, which is a piece of cake.
After doing this, developing our VHDL based on Matlab implementation is very straight forward.
Python language isn't a very common knowledge for people developing hardware, so they really need to learn a complete new language made to another domain (software) in order to do the same thing!
VHDL/Verilog has been used for 30 years and in my opinion will continue to be used for many mores, Python's language structure just doesn't have what's needed to the hardware domain.
I see myself wasting a lot of time having to teach our old hardware guys Python and how to think in terms of RTL with a new Language. That's why i didn't try to switch.
Remember, most of the engineers working with hardware come from EE background, not CS. They are more familliar with Schematics than C.
Re: MyHDL – Design hardware with Python – Examples
#29I don't know, i've been working with VHDL for 5 years and i don't see how this could be useful. Usually we first develop our algorithms using fixed point math at Matlab, which is a piece of cake. After doing this, developing our VHDL based on Matlab implementation is very straight forward. Python language isn't a very common knowledge for people developing hardware, so they really need to learn a complete new languag…
For design I agree. For verification, software techniques are often used and systemverilog has a lot of growing up to do.
Re: MyHDL – Design hardware with Python – Examples
#30I don't know, i've been working with VHDL for 5 years and i don't see how this could be useful. Usually we first develop our algorithms using fixed point math at Matlab, which is a piece of cake. After doing this, developing our VHDL based on Matlab implementation is very straight forward. Python language isn't a very common knowledge for people developing hardware, so they really need to learn a complete new languag…
This is extremely useful for people with CS backgrounds who want to get into CS. My first dive into VHDL was disasterous, I feel like it would have went much better if I had used something like this with a familiar syntax.