MyHDL – Design hardware with Python – Examples
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Re: MyHDL – Design hardware with Python – Examples
#2A related project is Chisel, in which you create language using Scala: https://chisel.eecs.berkeley.edu/
Re: MyHDL – Design hardware with Python – Examples
#3Always great to see new developments in HDLs.
It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation.
Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
Re: MyHDL – Design hardware with Python – Examples
#4Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
MyHDL is not bad for quick prototyping. The main problem I had was using vendor-supplied libraries in simulation, I needed to completely model the vendor block (timing and input-output) which is quite error prone.
OTOH, one of the nice things is the ease of moving from a numpy model of the system to RTL. And using PyPy for running simulations really makes MyHDL hum along quickly [0]
Re: MyHDL – Design hardware with Python – Examples
#5Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
SystemC is the C++ equivalent that's been around for a long time. For a project I was working on, I used SystemC just for system-level modelling, it didn't bother me that I couldn't synthesize. To achieve decent clock-rates it would have been a good idea to reimplement the whole thing in "native" Verilog anyway (though my project didn't get that far). What SystemC provided me with is a way to sanity-check my model at the "transaction" level.
Pretty cool to see this, and going forward as a roadmap there is much they could borrow from SystemC.
Re: MyHDL – Design hardware with Python – Examples
#6There is so much potential in open source hardware design.
Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware.
Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source software would still be in the dark ages.
I applaud any effort to advance the open source hardware design toolset.
Re: MyHDL – Design hardware with Python – Examples
#7Always great to see new developments in HDLs. It seems there is no synthesis (which is to be expected without vendor support). With 'limited' conversion to VHDL/Verilog, I wonder how useful this is for actual implementation. Also from the site I couldn't find any mention of higher level functionality such as generics, etc.
MyHDL has been and is being used for production designs.
For parametrizability, you have the full Python power at your disposal. This is also true for conversion, because conversion happens after elaboration of the design.
Re: MyHDL – Design hardware with Python – Examples
#8I've recently started writing my own HDL as an embedded language within Idris. The idea behind it is that you can take advantage of the rich type system and you have the option to prove theorems about your circuits to gain confidence in them. There are also bindings to picosat, so that you can automatically prove some properties. Here's a snippet of how it looks so far (though things are changing rapidly):
lt : BoolOperation op => Vect n v -> Vect n v -> SSA op v v
lt [] [] = constOp False
lt (x :: xs) (y :: ys) = do
nX Re: MyHDL – Design hardware with Python – Examples
#9A related project is Chisel, in which you create language using Scala: https://chisel.eecs.berkeley.edu/
Very happy to see both the projects (MyHDL and Chisel). I am not the target audience, but I was once interested in building some thing like this in Scala.
What is the uptake of Chisel in the target audience? I have observed that hardware designers that are not familiar with general programming language concepts don't appreciate the benefits of type-safe and object-oriented languages. Heck, even the software developer community is divided over the subject.
Re: MyHDL – Design hardware with Python – Examples
#10There is so much potential in open source hardware design. Right now, we are held back by (at best) mediocre tools. We need better HDL software, better synthesis software, better EDA software before we have any hope of widespread use of open source hardware. Imagine if the only compilers available were proprietary compilers locked behind hundreds of pages of licensing requirements and legal bullshit. Open source soft…
I think this is where FPGAs might prove very useful. Even if the designs made on FPGAs are small-scale, amateurish or sub-optimal today, they will help develop an ecosystem of tools, including open-source tools, that will ultimately help larger-scale open-source hardware.