61–70 of 74 posts
Enjoying the "DOS" font of the code examples. The wikipedia page on the Pentium has multiple references to an Intel publication called "Solutions", May/June 1993. It would be interesting to see that, but can't find a copy. https://en.wikipedia.org/wiki/Pentium_(original)#cite_note-1...
I will keep looking...
Earlier quoted context omitted.
> I believe that only the first Pentium 3 core, Katmai, did this. No, all Pentium 3s as well as the Pentium M. Pentium 4 notably didn't suffer from it, but it of course had many, many, MANY other performance issues. > I have some faint memories of hearing somewhere that Long Mode didn't support x87. I wonder if it is related to this early info you mention and it being Microsoft specific. It was VM86 mode that Long Mo…
> but it of course had many, many, MANY other performance issues. The whole RAMBUS debacle... OTH DDR chipsets for Tualatin had shown what it was the end game for the P6 arch.
> Each MMX register is 64 bits wide. Internally, the MMX registers were aliases of the x87 floating-point registers. Due to the way the first Pentium 3 CPUs (Katmai) were built, they likewise aliased the x87 (and thus, MMX) registers to the XMM SSE registers, but this was hidden from programs. It wasn't until at least the Coppermine revision that they were separate registers again.
I remember hearing a rumour as a young teen that the Coppermine codename meant it actually had copper wiring and that's what made it faster somehow. Copper has lower resistance than aluminium and can therefore help chips run faster - it makes sense! But it was just a codename and the coppermine had aluminium interconnects. My family got a PIII 533Mhz coppermine, in the early sideways Slot 1 configuration. Blazing fas…
I would add than SSE1 and SSE2 are now required parts of AMD64 instruction set. All 64-bit PC processors are required to support them both. For that reason, modern compilers are ignoring x87 FPU when building 64-bit binaries. Instead, they compile all float and double arithmetic into SSE1 and SSE2 instructions, respectively.
Which is not to say that they are necessarily auto-vectorizing. You know wassup when you see vaddsd instead of vaddpd. And ideally you'd use AVX-512 to saturate a modern cache line if you can afford to drop support for the older devices.
I still remember the MMX TV campaign they put out in the 90s. https://www.youtube.com/watch?v=5zyjSBSvqPc https://www.youtube.com/watch?v=cnEuWfFTuxg I was watching this and thinking "Who's going to even understand what this is about? Why is this playing on primetime TV?" Playing video on a computer wasn't a thing at the family consumer level at this time, and gaming was still a geeky niche.
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They were always required. IIRC early AMD64 CPUs did not support x87 instructions in long mode at all (causing #UD), and that support was Intel's extension in first EM64T CPUs.
Please refrain from making things up -- Long Mode has always supported x87. You may be mis-remembering LAHF/SAHF.
If you ever dug into x86 assembler programming... at first they make no sense at all. They only save/restore a tiny part of the available flag registers. The mnemonics themselves make little sense - load/store are not really used in any other base x86 mnemonics (unlike e.g. 6502 mnemonics, which use LD?/ST? instead of MOV like x86).
It only clicked when I read an Intel document about porting assembler code from the 8080 to the 8086.
LAHF/SAHF are basically convenience instructions to make porting easier. Many 8080 instructions did not alter the flags, unlike their 8086 counterparts. Substituting an `INX` instruction with `LAHF; INC; SAHF` made it possible to mechanically translate assembler source code.
And yeah, 8080 mnemonics had LDA and STA like the 6502...
Earlier quoted context omitted.
I remember hearing a rumour as a young teen that the Coppermine codename meant it actually had copper wiring and that's what made it faster somehow. Copper has lower resistance than aluminium and can therefore help chips run faster - it makes sense! But it was just a codename and the coppermine had aluminium interconnects. My family got a PIII 533Mhz coppermine, in the early sideways Slot 1 configuration. Blazing fas…
Ironically P.o.d. didn't really use MMX at all except for Dolby Surround decoding[1]. [1] https://retromediahub.com/index.php/Pod:_Planet_of_Death
Doesn't look like there's any conclusive info out there, so probably someone needs to actually decompile it and look for MMX opcodes.
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It’s more likely they’re confusing it with 3DNow! (AMD’s own media extension focused on floating point math). That was strictly aliased and therefore an either/or situation on chips that had both.
Sure, 3DNow! operated on MMX registers. But the OP was talking about Intel's P3... so 3DNow! wasn't a factor...
SSE never had aliasing, so OP’s comment is strictly incorrect either way.
Enjoying the "DOS" font of the code examples. The wikipedia page on the Pentium has multiple references to an Intel publication called "Solutions", May/June 1993. It would be interesting to see that, but can't find a copy. https://en.wikipedia.org/wiki/Pentium_(original)#cite_note-1...
I have looked -- no luck so far. I will keep looking...