51–60 of 74 posts
John Carmack promised that Quake II will use MMX, but this wasn't done. That's why software rendering in Quake II is so boring, it doesn't even support colored lighting. In the other hand Unreal did use MMX, which allowed it to work in 32-bit color mode with colored lighting and a bunch of other effects.
> Each MMX register is 64 bits wide. Internally, the MMX registers were aliases of the x87 floating-point registers. Due to the way the first Pentium 3 CPUs (Katmai) were built, they likewise aliased the x87 (and thus, MMX) registers to the XMM SSE registers, but this was hidden from programs. It wasn't until at least the Coppermine revision that they were separate registers again.
It makes it easier to save and restore state when it's basically the same registers used differently.
Go to page. Nothing. Enable Javascript for it. Still nothing. Enable more Javascript. Still nothing. Third lot of Javascript and now it finally renders. It's static text with a few images... that doesn't display until you tell NoScript to enable Javascript from a pile of third-party sites.
> Each MMX register is 64 bits wide. Internally, the MMX registers were aliases of the x87 floating-point registers. Due to the way the first Pentium 3 CPUs (Katmai) were built, they likewise aliased the x87 (and thus, MMX) registers to the XMM SSE registers, but this was hidden from programs. It wasn't until at least the Coppermine revision that they were separate registers again.
No, x87/MMX and SSE XMM were not aliased. They were two separate register files. (You may be confusing it with XMM vs YMM vs ZMM, i.e. SSE vs AVX vs AVX512.)
Enjoying the "DOS" font of the code examples. The wikipedia page on the Pentium has multiple references to an Intel publication called "Solutions", May/June 1993. It would be interesting to see that, but can't find a copy. https://en.wikipedia.org/wiki/Pentium_(original)#cite_note-1...
https://int10h.org/oldschool-pc-fonts/readme/
I would add than SSE1 and SSE2 are now required parts of AMD64 instruction set. All 64-bit PC processors are required to support them both. For that reason, modern compilers are ignoring x87 FPU when building 64-bit binaries. Instead, they compile all float and double arithmetic into SSE1 and SSE2 instructions, respectively.
> Each MMX register is 64 bits wide. Internally, the MMX registers were aliases of the x87 floating-point registers. Due to the way the first Pentium 3 CPUs (Katmai) were built, they likewise aliased the x87 (and thus, MMX) registers to the XMM SSE registers, but this was hidden from programs. It wasn't until at least the Coppermine revision that they were separate registers again.
I remember hearing a rumour as a young teen that the Coppermine codename meant it actually had copper wiring and that's what made it faster somehow. Copper has lower resistance than aluminium and can therefore help chips run faster - it makes sense! But it was just a codename and the coppermine had aluminium interconnects. My family got a PIII 533Mhz coppermine, in the early sideways Slot 1 configuration. Blazing fas…
I would add than SSE1 and SSE2 are now required parts of AMD64 instruction set. All 64-bit PC processors are required to support them both. For that reason, modern compilers are ignoring x87 FPU when building 64-bit binaries. Instead, they compile all float and double arithmetic into SSE1 and SSE2 instructions, respectively.
They were always required. IIRC early AMD64 CPUs did not support x87 instructions in long mode at all (causing #UD), and that support was Intel's extension in first EM64T CPUs.
You may be mis-remembering LAHF/SAHF.
Earlier quoted context omitted.
No, x87/MMX and SSE XMM were not aliased. They were two separate register files. (You may be confusing it with XMM vs YMM vs ZMM, i.e. SSE vs AVX vs AVX512.)
It’s more likely they’re confusing it with 3DNow! (AMD’s own media extension focused on floating point math). That was strictly aliased and therefore an either/or situation on chips that had both.
But the OP was talking about Intel's P3... so 3DNow! wasn't a factor...
Earlier quoted context omitted.
> I believe that only the first Pentium 3 core, Katmai, did this. No, all Pentium 3s as well as the Pentium M. Pentium 4 notably didn't suffer from it, but it of course had many, many, MANY other performance issues. > I have some faint memories of hearing somewhere that Long Mode didn't support x87. I wonder if it is related to this early info you mention and it being Microsoft specific. It was VM86 mode that Long Mo…
>> I believe that only the first Pentium 3 core, Katmai, did this. > No, all Pentium 3s as well as the Pentium M. Pentium 4 notably didn't suffer from it, but it of course had many, many, MANY other performance issues. I had to google a bit to confirm this, and seems like I'm not the only one that understood it the way I did: https://www.vogons.org/viewtopic.php?p=1360606#p1360606 https://www.vogons.org/viewtopic.php…
You see, when two orders are possible, of course Intel had to ship both.
Yeeep, P3 vs P4. Which used which, is left as an exercise to you, dear reader.