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A third world engineer responds to “RISC-V: They should have known better”

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Re: A third world engineer responds to “RISC-V: They should have known better”

#91

Post by pixelesque »

whateverboat wrote: post #85
ndiddy wrote: post #66

I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…

The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion. And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.

> really crazy optimizations that they are doing

Any examples of this?

Re: A third world engineer responds to “RISC-V: They should have known better”

#92

Post by ip26 »

Ericson2314 wrote: post #88

My perspective using Nix is that it's hardly worth standardizing ISAs. Recompiling software is easy and we should have a Cambrian explosion of different designs. This is especially good if one scopes out a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA.

What exactly does a bespoke ISA buy you? What will justify hundreds of engineers writing a new good one & working through the compiler support?

I bet it would be pretty easy for a user to interoperate between 67 different drafts of the HTTP spec once they were all written, validated, and library implementations coded. But what would that Cambrian explosion of API revs actually get you?

Re: A third world engineer responds to “RISC-V: They should have known better”

#93

Post by gertop »

MBCook wrote: post #45
Lagoon3384_SWE wrote: post #28

[flagged]

So “you were born somewhere ‘unlucky’, that’s how it goes, sucks to be you”. Is that really your take?

It's a distasteful take to be sure. But, what is GP supposed to do?

Frankly I'd rather be told that than the other common but tired SV-resident take of "just hustle, bro, stop sleeping, hustle hustle hustle. Learn to code, take loans from friends and family. Doesn't matter that you're born in a shithole, I was born in a median family myself, we only had one car and we rented our house!!! Just gotta work for it, everybody can achieve it. Those who don't, are clearly not working hard enough."

Re: A third world engineer responds to “RISC-V: They should have known better”

#94

Post by Conan_Kudo »

initramfs wrote: post #90
Conan_Kudo wrote: post #89

Earlier quoted context omitted.

I'll also point out that we've always had better starting points for open source high performance cores. SPARC and POWER both have open ISAs and open-source cores with useful performance. The UltraSPARC T1 and T2 processors were open sourced under the OpenSPARC project. POWER has the OpenPOWER project governing the Power ISA, and IBM itself created Microwatt, Chiselwatt, and the A2I/A2O cores as open source that peop…

True, and the only reason I'm partial to x86 and even some older ARMv cores is that there is a huge existing software ecosystem already available, reducing the need to develop new bootloaders and ports, as coding hours aren't free. CISC cores are treated as if they are a dirty word, but are more versatile for covering various applications.

PowerPC at least still has a living ecosystem, even from the bootloader level. GRUB can boot from an OpenFirmware system. There's also yaboot if you hate yourself. ;)

I would personally love to see more Power Systems based projects. Everything is out there, just someone has to want to do something with it.

Fedora Linux even fully supports POWER8+ little-endian systems, and Fedora KDE offers a live ISO you can install on something like a Talos Workstation.

Re: A third world engineer responds to “RISC-V: They should have known better”

#95

Post by kazinator »

> He derives the case for the chip and then spends the rest of the article annoyed that the chip exists. This is almost satirical.

His criticisms are entirely valid, because why can't the the thing that has a free spec and will likely dominate that space ... also be good too? Can't we have all the nice things?

Re: A third world engineer responds to “RISC-V: They should have known better”

#96

Post by Animats »

Sha1rholder wrote: post #13

Nice read! Though it feels a bit strange that "I have exceeded the allowed number of requests. (500 times)" when I first clicked the article and I'm pretty sure I don't share the ip of my self-hosted VPN with anyone.

I got that too and couldn't read the site.

Re: A third world engineer responds to “RISC-V: They should have known better”

#97

Post by articulatepang »

spacechild1 wrote: post #49
cyberclimb wrote: post #35

Earlier quoted context omitted.

I don't think they are necessarily asserting otherwise

So what does it mean to ship from Asia to Bangladesh? Do you ship from India, Iran or Indonesia? Or just within Bangladesh? :)

In the context of microcontrollers and electronics, the likeliest intended meaning was shipping from China, South Korea, Taiwan and perhaps Japan, because that’s where the bulk of the fabs are.

Re: A third world engineer responds to “RISC-V: They should have known better”

#98

Post by yjftsjthsd-h »

whateverboat wrote: post #85
ndiddy wrote: post #66

I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…

The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion. And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.

> The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion.

I assume this is addressing

> and since all the RISC-V SBCs I'm aware of have significantly worse performance and efficiency than comparably priced ARM SBCs.

If so, could you point at specific SBCs that beat ARM SBC perf?

Re: A third world engineer responds to “RISC-V: They should have known better”

#99

Post by PunchyHamster »

pixelesque wrote: post #91
whateverboat wrote: post #85

Earlier quoted context omitted.

The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion. And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.

> really crazy optimizations that they are doing Any examples of this?

There aren't ones that wouldn't be served better by ARM

The improvement is entirely "we don't have to pay ARM"

Re: A third world engineer responds to “RISC-V: They should have known better”

#100

Post by egypturnash »

Rate Limit Exceeded Too Many Requests

You have exceeded the allowed number of requests. Your Requests: 500. Request Limit: 500 per minute. Tip: Please wait 60 seconds before trying again.

A 3rd World Embedded Engineer Learns About Caching Generated HTML The Hard Way.

https://archive.md/9FaRC

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