More than half the article is AI slop. Sad.
A third world engineer responds to “RISC-V: They should have known better”
81–90 of 350 posts
Re: A third world engineer responds to “RISC-V: They should have known better”
#82Earlier quoted context omitted.
This is a bay area centric take on a non bay area centric take. The typical bay area centric take has the following vibe: 1. I am among the group of most open minded people 2. I admit mistakes, but I don't change my view, that means I may make the same mistakes next time on a different concrete cases 3. Morally I am among the least corrupted 4. I work for the moderately morally questionable firms with nice paychecks,…
As exemplified in the following series of essays https://www.astralcodexten.com/p/the-foothills-of-bay-area-h...
Thank you so much for sharing these. I just laughed my ass off a bunch, and I’ve only yet read this one latest post in the series.
My favorite bit, I think (along with the running gag of the constant use cases/connections that somehow pop up for Epstart’s founder):
> “Would you like to hear more about how copying AI tics helps me keep conversations going?”
> “Uh, sure - wait! No!” You break off and turn around as fast as you can.
If the other entries in the series are anywhere near as good, I’ll have some reading to do now.
Re: A third world engineer responds to “RISC-V: They should have known better”
#83I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…
Different RISC-V dialects might as well be as different from each other as English is from German. Sure, the cognates, family the resemblance, and common(-ish) alphabet make some things easier, but if you're shipping a manual, you still need to do it both in English and auf Deutsch unless you rely on machine translation.
So it is with the family of mutually incomprehensible ISAs called RISC-V.
Re: A third world engineer responds to “RISC-V: They should have known better”
#84He says: > From that position, the difference between a ten cent part and a one dollar part is not a rounding error and it is not a detail you get to wave past on the way to the interesting discussion about encodings Yet earlier: > I pay anywhere from US $60 to US $200 to ship one dollar chips that people everywhere else get free shipping on Seems to me that the difference between a 10c chip and a $1 chip are a round…
I’d really like an explanation here if the author is reading. And how does shipping cost scale with quantity? Can you get that to be small per unit on big orders?
Re: A third world engineer responds to “RISC-V: They should have known better”
#85I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…
The huge number of companies building RISC-V chips and really crazy optimizations that they are doing in all kinds of spaces are a very real counterweight to your notion.
And RISC-V is just starting here with shoestring design and fab budget. Wait till all engineering teams really adopt it like Tenstorrent and NextSilicon and so on.
Re: A third world engineer responds to “RISC-V: They should have known better”
#86I think he's kind of speaking past the original author. The original piece is basically about how the author doesn't think that RISC-V will take off outside embedded, because of some design decisions that lead to poor performance compared to ARM64 and because so much of the ISA being optional means that there's too much fragmentation to make binary distribution feasible. Meanwhile, this piece is mainly about how RISC…
> Personally I don't see the benefit of this since you're going to have to recompile your software anyway
The benefit is a unified toolchain. Make a chip, get the entire software toolchain for free.
In the past if you made your own chip you had to write your own assembler, compiler, debugger, etc. Many manufacturers forked gcc but of course it's still a lot of work and the license isn't great (for them, not the user).
This universal compiler toolchain is massive benefit for both the chip makers and the end user.
Re: A third world engineer responds to “RISC-V: They should have known better”
#87To me it feels like the difference in positions is "this could be made better" vs. "but this is already so much better than before". Both are right. Maybe I'm missing something important so far...
Maybe. I'm not sure if the original author's intent was to say how risc-v could be better or to say it is bad and people should use other (proprietary) ISAs instead.
Re: A third world engineer responds to “RISC-V: They should have known better”
#88My perspective using Nix is that it's hardly worth standardizing ISAs. Recompiling software is easy and we should have a Cambrian explosion of different designs.
This is especially good if one scopes out a family of ISAs that are ABI compatible such that one can compile down to a semi-pre-optimized portable IR, and just do the last bit per ISA.
Re: A third world engineer responds to “RISC-V: They should have known better”
#89Earlier quoted context omitted.
There are 386 and 486 open source reimplementations in Verilog (see z386 and z486). As far as I know, existing commercial 386/486 chips still manufactured (yes they exist!) are descendants of Cyrix work, not Intel or AMD. Consequently, VIA may be contractually holding those back rather than Intel/AMD doing anything there.
Thanks for that information! I have been interested in getting x86 produced in smaller nanometer (e.g. https://ei2030.github.io/FemtoTX/#about Edit: It also appears Nvidia might also have an x86 license: https://www.nvidia.com/en-us/drivers/uli-m6117c/ Also, https://www.tomshardware.com/pc-components/cpus/intel-licens... (Caveat: The startup is acquainted with the Intel CEO, so it's rare for them to grant the x86 lic…
I'll also point out that we've always had better starting points for open source high performance cores. SPARC and POWER both have open ISAs and open-source cores with useful performance. The UltraSPARC T1 and T2 processors were open sourced under the OpenSPARC project. POWER has the OpenPOWER project governing the Power ISA, and IBM itself created Microwatt, Chiselwatt, and the A2I/A2O cores as open source that people can build their own PowerPC systems from.
OpenFirmware came out of OpenSPARC and is also used by POWER too. Parts of it are used in ARM and RISC-V today (mostly DeviceTree, though arguably quite badly).
Nobody actually wants to make good cores for cheap. Nobody wants to make compatible systems unless forced to. That's why ARM and RISC-V are fragmented messes.
Re: A third world engineer responds to “RISC-V: They should have known better”
#90Earlier quoted context omitted.
Thanks for that information! I have been interested in getting x86 produced in smaller nanometer (e.g. https://ei2030.github.io/FemtoTX/#about Edit: It also appears Nvidia might also have an x86 license: https://www.nvidia.com/en-us/drivers/uli-m6117c/ Also, https://www.tomshardware.com/pc-components/cpus/intel-licens... (Caveat: The startup is acquainted with the Intel CEO, so it's rare for them to grant the x86 lic…
I'll also point out that we've always had better starting points for open source high performance cores. SPARC and POWER both have open ISAs and open-source cores with useful performance. The UltraSPARC T1 and T2 processors were open sourced under the OpenSPARC project. POWER has the OpenPOWER project governing the Power ISA, and IBM itself created Microwatt, Chiselwatt, and the A2I/A2O cores as open source that peop…
True, and the only reason I'm partial to x86 and even some older ARMv cores is that there is a huge existing software ecosystem already available, reducing the need to develop new bootloaders and ports, as coding hours aren't free. CISC cores are treated as if they are a dirty word, but are more versatile for covering various applications.