Always good to see stuff from Dmitry; his presentation (Linux/4004) at last year’s Teardown was awesome.
RISC-V: They Should Have Known Better
101–110 of 467 posts
Re: RISC-V: They Should Have Known Better
#102Earlier quoted context omitted.
x86 chips don't truly exist anymore. They only use it as a compressed ISA for a more capable internal representation that can be freely updated at any time.
This is a load of bullshit that largely exists as copium to explain how x86 did the impossible and made a superscalar CISC processor. x86 is doing the same thing that (to my knowledge) all high-end processors do, yet no one tries to call out those chips as compiling to a different internal ISA. But you also don't see any chips trying to run with multiple ISA modes: the closest you get is 32-bit and 64-bit modes coexi…
Amen. I remember the about 6 months when the benchmark cawboys were screaming that they had to be able to have access to directly program the Pentium Pro micro-instructions because 'that would be so much faster' and no matter how much the Intel architects who actually knew how things worked said "I don't think those words mean what you think they mean" there was some conspiracy to keep the PPro from achieving it's max performance...as if Intel didn't want the PPro to show it's max performance.
Humans are weird.
Re: RISC-V: They Should Have Known Better
#103It's basically MIPS all over again The conclusion is honest, and you can of course brute force any ISA into any role. I used to loathe x86 for that reason, but now that I'm older I respect the game.
X86 is the best argument that you can build a fast efficient RISC-V chip... because the X86 instruction set is a much bigger mess. It just blows my mind sometimes when designers don't learn insanely obvious lessons from the past, basic stuff like "complexity is evil" and "make the fast path overlap with the most common use cases" and "a standard with N optional extensions is actually N! (N factorial) standards." That…
> because the X86 instruction set is a much bigger mess.
One of the things I've been playing with off and on in my spare time is poking at the x86 ISA. And yet, while the ISA does have some weirdness to it, it is a lot less weird than its reputation makes it out to be. For example, the sum total of the opcode form amounts to does-it-have-ModR/M + size of immediate operand (in bytes)... which honestly strikes me as simpler than RISC-V instruction form decoding.
I know there's an earlier criticism of RISC-V that points out that one of the common instruction sequences for which "macro-op fusion" is the suggested solution involves 5 instructions... and I don't think any of the existing chips ever fuse more than 3 instructions?
Re: RISC-V: They Should Have Known Better
#104> Say you want to store a byte to a register plus offset. What range of offsets can a [compressed] 16-bit instruction encode? Zero through three.
If a compressed instruction could load or store a word to a word-scaled offset 0-3, relative to a register base address, that would be quite useful. It could be used for accesses to all structures four words or smaller.
Re: RISC-V: They Should Have Known Better
#105Earlier quoted context omitted.
I don’t think making optional what optional features are available is a little mistake. It is a torpedo to the waterline.
It's not. In practice you have two scenarios: 1. You have a microcontroller. You're compiling code yourself and the docs tells you what features are available and which compiler flags to use. 2. You are writing application code. In that case you simply target RVA23. The edge case is the same edge case where you use CPUID on x86, I.e. you want to target say RVA23 and RVA28 in the same binary. In that case you do have…
When I looked into mconfigptr some years ago I thought it looked like a swirling vortex of pain that might produce something useful some day. Good to see it's still being worked on. Sad to hear ASN.1 is still involved.
I added an "misa but more bits" register to my core, using the bit assignment from the RISC-V C API, so at least until then I know what extensions each instance of my core implements. https://wren.wtf/hazard3/doc/#reg-h3.misa
Linux folks seem to have already put a lot of the mconfigptr info into the DT blob anyways.
Re: RISC-V: They Should Have Known Better
#106Earlier quoted context omitted.
Noone uses an 8051 because it's elegant. Billions are still still sold every year because no matter if you learned it in the 70s or last week and no matter who made it, the basics are exactly alike. Software matters; ISAs don't.
Every time I've seen someone use an 8051 in the past twenty years, it's had new, bespoke software written for it. They were more used because they were a known quantity with the patents obviously dead rather than support for existing codebases.
Interesting comment. I suspect without solid facts that new bespoke stuff is mostly either 1) some ARM variant, or 2) some rando US$0.001 Chinese uproc. I think 8051 survives because there's many decades of experience using it, but as I understand the cool kids going into embedded don't think the boomers 8051 is fun and the pool of talent is shrinking fast. SO we'll see what the future holds.
Re: RISC-V: They Should Have Known Better
#107[deleted]
Re: RISC-V: They Should Have Known Better
#108Earlier quoted context omitted.
Every time I've seen someone use an 8051 in the past twenty years, it's had new, bespoke software written for it. They were more used because they were a known quantity with the patents obviously dead rather than support for existing codebases.
Interesting comment. I suspect without solid facts that new bespoke stuff is mostly either 1) some ARM variant, or 2) some rando US$0.001 Chinese uproc. I think 8051 survives because there's many decades of experience using it, but as I understand the cool kids going into embedded don't think the boomers 8051 is fun and the pool of talent is shrinking fast. SO we'll see what the future holds.
Those aren't mutually exclusive. Some of the sophgo and bouffalo chips have 8051s for always on cores, and riscv for the main cores.
They didn't choose 8051 there for experience, but because it was a tiny core with a decent IPC they could license for a small part, then focus on the main cores. I wouldn't be surprised if they eventually switch to riscv there too.
Also, these 8051 cores tend to be extremely diverse. I don't think I've come across cores from different manufacturers that were actually compatible for real code. They all seem to want to handle accessing 16/32 bit memory differently, have different interrupt details, etc.
Re: RISC-V: They Should Have Known Better
#109Earlier quoted context omitted.
> "RISC-V is already dominant in the MCU space[...]" Where are you getting the idea that RISC-V is dominant? As someone who works in this space, that doesn't jive with my experience or the sources I've seen.[1] 32-bit microcontrollers only recently achieved a majority market share for gosh sakes! RISC-V is claiming that they have achieved 25% market share across selected segments, but they're still behind ARM (and x8…
Risc-v is nowhere near dominant, people are just being swayed by headlines such as Western Digital or Nvidia shipping billions of risc-v cores. I do find it odd that you go on and compare to x86 marketshare however, the topic you've quoted is very clearly about MCU and whilst 8086 MCU still exists they haven't been used in greenfield projects for decades. Let alone any more recent x86 implementation.
Because it's in stuff where you don't see it: in your vacuum cleaner, your toaster oven, your microwave or your electric kettle.
Do you really think Chinese manufacturers are going to buy ARM MCUs when their budget for a controller is less than 10 cents?
ARM has long ceded this market to RISC-V. It's mostly focusing on high-end application MCUs and AI now.
And lots of newer stuff is making use of standardized boards like Raspberry Pi Pico (RISC-V and ARM hybrid) or ESP32 (RISC-V too on some versions).
Re: RISC-V: They Should Have Known Better
#110Earlier quoted context omitted.
Interesting comment. I suspect without solid facts that new bespoke stuff is mostly either 1) some ARM variant, or 2) some rando US$0.001 Chinese uproc. I think 8051 survives because there's many decades of experience using it, but as I understand the cool kids going into embedded don't think the boomers 8051 is fun and the pool of talent is shrinking fast. SO we'll see what the future holds.
Those aren't mutually exclusive. Some of the sophgo and bouffalo chips have 8051s for always on cores, and riscv for the main cores. They didn't choose 8051 there for experience, but because it was a tiny core with a decent IPC they could license for a small part, then focus on the main cores. I wouldn't be surprised if they eventually switch to riscv there too. Also, these 8051 cores tend to be extremely diverse. I…
Interesting...I don't know much about sophgo and bouffalo chips. Not surprising since the 8051 is patent-free these days. Something I found crazy is how many places someone embedded an 8051 core. Like the tire pressure monitor in every tire these days. Fun stuff.