> Chip Design > As an early proof of concept, Kimi K3 designed a chip to serve a nano model built on its own architecture. In a single 48-hour autonomous run, K3 built, optimized, and verified the chip using open-source EDA tools on the Nangate 45nm library. Within 4 mm², the chip closes timing at 100 MHz and sustains over 8,700 tokens/s decode throughput in simulation, packing 1.46M standard cells, 0.277 MB of SRAM,…
I had a thought a while back: sell large local models burned onto fused compute / ROM chips. Like cartridges for old game consoles. Slot (or probably plug into USB-C) and go. It’s an ASIC with the model wired into it so it’s very low power and fast. I’d buy these. Say $100 for a frontier class model. Maybe more.
It's not as simple as a weight swap between identical architectures.
The speed gains are also from not having to route the weights through wiring like with ROM cartridges.