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RISC-V Is Inevitable: State of the Union Keynote Argues

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Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#41

Post by throawayonthe »

SanjayMehta wrote: post #16
ColdStream wrote: post #2

It was a decent little talk this one. Now that we are seeing RVA23 chips available we are starting to at least see a lot of software packages actively compiled for the platform. They aren't optimized much at all but they do run. I am cautiously optimistic about the future of RISC-V. It is likely to start biting at the heals of ARM in another 5 years or so, and having no licensing fees makes it very attractive in that…

5 years ago there was a req on the Apple job site for engineers familiar with RISC-V. https://riscv.org/blog/apple-exploring-risc-v-hiring-risc-v-...

tbf apple does a bunch of embedded programming too

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#43

Post by cold_pizz4 »

incrudible wrote: post #14
rwmj wrote: post #7

Earlier quoted context omitted.

Krste wasn't even saying anything controversial. It's obvious that manufacturers will use the cheapest (free) least legally entangled option, and that this adoption will happen first amongst those with the tightest margins. And - Clayton's law[1] - it will eventually extend to the rest of the market (albeit over a very long time). https://en.wikipedia.org/wiki/Clayton_Christensen

The good RISC-V designs are not free though and the free ones are not good. MCUs are not a category of computer to draw lessons from for the broader market.

Wait a few years until a RISC-V Fab as a Service emerges and any teenager with an LLM can design and order their own chips ;)

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#44

Post by tpxl »

red_admiral wrote: post #42

My money is still on ARM. They, and their clients who produce the actual processors, have options to fight back if RISC-V ever becomes a serious competitor for, say, smartphones.

What options are those? Anything they do that makes ARM better/cheaper for consumers makes RISC-V a win, even if it never reaches mainstream adoption.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#45

Post by theturtletalks »

tpxl wrote: post #44
red_admiral wrote: post #42

My money is still on ARM. They, and their clients who produce the actual processors, have options to fight back if RISC-V ever becomes a serious competitor for, say, smartphones.

What options are those? Anything they do that makes ARM better/cheaper for consumers makes RISC-V a win, even if it never reaches mainstream adoption.

Exactly why every user of a product should be an strong supporter of the competitor. It's what keeps your product honest and competition is good for the consumer.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#46

Post by unprovable »

jhvkjhk wrote: post #10

> “CHERI is not an extension; CHERI is a new base,” Asanović clarified to the keynote audience. > Addressing concerns that creating a new base ISA might fracture the open-source community, Asanović offered a devoted defense to EE Times. “CHERI is too invasive to be a simple extension on regular RISC-V, and so needs a new base ISA for that reason,” To me it sounds like they're creating RISC-VI before RISC-V even winni…

I've been trying to get access to CHERI for quite a while - I have a background in hardware security so was very curious to have a play. But only 'approved partners' are allowed to have access... guessing even in projects like this, Security through Obscurity still reigns.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#47

Post by seastarer »

camel-cdr wrote: post #22
modulovalue wrote: post #8

I'm working on making SIMD better in Dart. Dart supports RISC-V as a target architecture for compilation, but I'm not really excited about figuring out how to map the wasm-SIMD-style primitives to RISC-V's RVV and so I don't really plan to look into it at all. This is mostly because their approach to SIMD is so different, but also because I can't test it at all. Are there any RISC-V "machines"? that one can use to do…

> Dart supports RISC-V as a target architecture for compilation, but I'm not really excited about figuring out how to map the wasm-SIMD-style primitives to RISC-V's RVV and so I don't really plan to look into it at all. On the one hand, this will be quite straight forward, but on the other hand quite disappointing. Afaik Dart has a 128-bit only SIMD abstraction (so not performance portable by default). Since the base…

You can try to re-vectorize the code for larger vector size.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#48

Post by crote »

imtringued wrote: post #37
rwmj wrote: post #31

Earlier quoted context omitted.

ARM and Microsoft don't "care" enough to do anything beyond a bit of token research. Maybe there will be some extremely niche chips one day, or maybe not because the problem can be solved 90% as well in software on ordinary hardware.

Microsoft and Apple will probably switch to CHERI RISC-V for their Secure Enclave/TPMs once it has proven itself in the field. That means there will be hundreds of millions of CHERI RISC-V processors in the world. Not to mention the smartcard market which would mean billions of processors around the world.

The Intel Management Engine famously runs MINIX. Tanenbaum has called it "the most widely used computer operating system in the world" - but it hasn't exactly led to mainstream MINIX adoption.

Smartcards often run Java Card, which solves the whole memory safety problem the other way around. You don't need CHERI for this kind of limited platforms: want to run memory-safe C today? Just ban all dynamic memory allocations. Throw in the usual UB restrictions and stick to a single thread and very little can go wrong.

What's important to remember is that, despite its large deployment figures, those are still niche applications. The number of people developing for them is a rounding error. There is no clear path from there to mainstream adoption.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#49

Post by speed_spread »

thrownawaysz wrote: post #40

If we go by Apple's architecture history we will get a new one, maybe RISC-V, in 2036. m68k (1984) > PPC (1994) - 10 years PPC (1994) > x86 (2006) - 12 years x86 (2006) > ARM64 (2020) - 14 years ARM64 (2020) > ??? (2036) - 16 years

Except that ARM is pretty much theirs, or at least they have complete control over it, which they never did for any previous arch. They also handle chip production directly. Nothing in RISC-V could be worth more than what they can already wring out of ARM without having to migrate.

Re: RISC-V Is Inevitable: State of the Union Keynote Argues

#50

Post by diamondlovesyou »

seastarer wrote: post #47
camel-cdr wrote: post #22

Earlier quoted context omitted.

> Dart supports RISC-V as a target architecture for compilation, but I'm not really excited about figuring out how to map the wasm-SIMD-style primitives to RISC-V's RVV and so I don't really plan to look into it at all. On the one hand, this will be quite straight forward, but on the other hand quite disappointing. Afaik Dart has a 128-bit only SIMD abstraction (so not performance portable by default). Since the base…

You can try to re-vectorize the code for larger vector size.

Not if you can't prove anti-aliasing properties, which wasm doesn't carry.
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