RISC-V Is Inevitable: State of the Union Keynote Argues
1–10 of 142 posts
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#2It was a decent little talk this one. Now that we are seeing RVA23 chips available we are starting to at least see a lot of software packages actively compiled for the platform. They aren't optimized much at all but they do run.
I am cautiously optimistic about the future of RISC-V. It is likely to start biting at the heals of ARM in another 5 years or so, and having no licensing fees makes it very attractive in that sense. Qualcomm and Apple will be very interesting in avoiding as many ARM licensing fees as possible even if initially in embedded systems. But it also allows for a lot of hardware to be locked down just like ARM and so it might not be so great for the end users. Time will tell.
All I know is that I look for the seeing Apple Silicon 2 launching in 2036 using this stuff. ;)
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#3It was a decent little talk this one. Now that we are seeing RVA23 chips available we are starting to at least see a lot of software packages actively compiled for the platform. They aren't optimized much at all but they do run. I am cautiously optimistic about the future of RISC-V. It is likely to start biting at the heals of ARM in another 5 years or so, and having no licensing fees makes it very attractive in that…
Can you elaborate on
> But it also allows for a lot of hardware to be locked down just like ARM
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#4While the consumer market is still years away from widespread RISC-V adoption, if you pay attention to the embedded / MCU market (especially Espressif & co) you will indeed come to the conclusion that RISC-V is inevitable and software maturity will probably come from these early adopters.
Go!
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#5It was a decent little talk this one. Now that we are seeing RVA23 chips available we are starting to at least see a lot of software packages actively compiled for the platform. They aren't optimized much at all but they do run. I am cautiously optimistic about the future of RISC-V. It is likely to start biting at the heals of ARM in another 5 years or so, and having no licensing fees makes it very attractive in that…
Can you elaborate on > But it also allows for a lot of hardware to be locked down just like ARM
[dead]
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#6It was a decent little talk this one. Now that we are seeing RVA23 chips available we are starting to at least see a lot of software packages actively compiled for the platform. They aren't optimized much at all but they do run. I am cautiously optimistic about the future of RISC-V. It is likely to start biting at the heals of ARM in another 5 years or so, and having no licensing fees makes it very attractive in that…
Can you elaborate on > But it also allows for a lot of hardware to be locked down just like ARM
Many of the underlying IP areas of RISK-V advanced features are not public implementations.
Yet there are still a lot of great projects around, that may end up in China grey market chip fabs (C950) at some point.
https://github.com/vortexgpgpu/vortex
ARM64/AArch64 is about constrained consistency, but most RISCV standards groups still fail to recognize their ISA version fragmentation was a serious mistake. So no, it won't exist outside niche use-cases until the kids stop arguing over what RISCV even means in a general end-user context (BOOM flags, RVA23, etc.) =3
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#7While the consumer market is still years away from widespread RISC-V adoption, if you pay attention to the embedded / MCU market (especially Espressif & co) you will indeed come to the conclusion that RISC-V is inevitable and software maturity will probably come from these early adopters. Go!
Krste wasn't even saying anything controversial. It's obvious that manufacturers will use the cheapest (free) least legally entangled option, and that this adoption will happen first amongst those with the tightest margins. And - Clayton's law[1] - it will eventually extend to the rest of the market (albeit over a very long time).
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#8I'm working on making SIMD better in Dart. Dart supports RISC-V as a target architecture for compilation, but I'm not really excited about figuring out how to map the wasm-SIMD-style primitives to RISC-V's RVV and so I don't really plan to look into it at all.
This is mostly because their approach to SIMD is so different, but also because I can't test it at all. Are there any RISC-V "machines"? that one can use to do something useful or fun with that someone here could recommend?
I guess it would be fun seeing all my SIMD-fiable use-cases become orders of magnitude faster on RISC-V, too, but I sadly never hear anything about machines that use RISC-V.
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#9It was a decent little talk this one. Now that we are seeing RVA23 chips available we are starting to at least see a lot of software packages actively compiled for the platform. They aren't optimized much at all but they do run. I am cautiously optimistic about the future of RISC-V. It is likely to start biting at the heals of ARM in another 5 years or so, and having no licensing fees makes it very attractive in that…
We still have to see a RISC-V implementation that comes even close to the performance of ARM
Re: RISC-V Is Inevitable: State of the Union Keynote Argues
#10> “CHERI is not an extension; CHERI is a new base,” Asanović clarified to the keynote audience.
> Addressing concerns that creating a new base ISA might fracture the open-source community, Asanović offered a devoted defense to EE Times. “CHERI is too invasive to be a simple extension on regular RISC-V, and so needs a new base ISA for that reason,”
To me it sounds like they're creating RISC-VI before RISC-V even winning the market.