131–140 of 217 posts
Keep hearing that IBM makes these incredible chips but don’t see anyone using IBM chips. What do they do with them?
Their line of POWER chips are used in their mainframes
https://en.wikipedia.org/wiki/Z/Architecture
IBM sells huge servers with POWER architecture CPUs but they are not what people are referring to when they talk about IBM mainframes.
GF did not pay IBM. IBM paid GF to take the fabs away.
https://www.reuters.com/article/technology/ibm-to-pay-global...
Earlier quoted context omitted.
Who started it?
https://www.eejournal.com/article/no-more-nanometers/ Sometime around 2011 when Intel named their process node 22nm which the gate length was 26nm
>So essentially, since 1997, the node name has not been a representation of any actual dimension on the chip, and it has erred in both directions by almost a factor of 2.
How does IBM commercialize this? Do they license this out to fabs?
I’m sure they will license it. It’s better for them if everyone in the industry can innovate on everything around it. All the process tech companies will make it more cost effective, for instance, which helps IBM as well.
Earlier quoted context omitted.
So the title should be corrected. The did not debut sub nm chips at all.
That ship sailed long ago. I think it was around 32nm-22nm node when the marketing term started diverging from the physical feature size.
Remember that IBM paid Global Foundries $1.5 billion to take their fabs and design services group. GF did not pay IBM. IBM paid GF to take the fabs away. https://www.reuters.com/article/technology/ibm-to-pay-global...
> IBM sees a path to production in as early as the next 5 years.
5 years is a long time for a product roadmap, so there are probably some significant unsolved problems remaining, and the timeline depends on whether IBM can solve these problems.
Earlier quoted context omitted.
> It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area. "Planar" and "3D" in this context refers to the shape of the transistors themselves. In a planar transistor the functional structure is spread out in the area, like this: https://en.wikipedia.org/wiki/File:MOSFET_functioning_body.s... wh…
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Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.
Why not use something absolute, like nand-gates per volume?
MTr/mm = 0.6×(NAND2 Tr Count)/(NAND2 Cell Area) + 0.4×(Scan Flip Flop Tr Count)/(Scan Flip Flop Cell Area)
> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…