IBM debuts sub-1 nanometer chip technology • Hacker News Board

Re: IBM debuts sub-1 nanometer chip technology

#111

Post by jayd16 » Thu, Jun 25, 2026, 8:49 PM UTC

u1hcw9nx wrote: post #85

buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Why not use something absolute, like nand-gates per volume?

Re: IBM debuts sub-1 nanometer chip technology

#112

Post by AlexCoventry » Thu, Jun 25, 2026, 8:55 PM UTC

Barrin92 wrote: post #73

alexey-salmin wrote: post #70

The most surprising part for me is that IBM still somehow owns silicon labs, I was sure it's effectively a consulting company by now

IBM has been the company with the most patent registrations in the US for I think 29 of the last 30 years. They're one of the largest industrial research organizations in the world. They're doing more hard science research than almost anyone else.

It's just a shame that none of it seems to pan out, and in the areas where I know what they're talking about, it all sounds like cynical nonsense to me.

Re: IBM debuts sub-1 nanometer chip technology

#113

Post by mikepurvis » Thu, Jun 25, 2026, 8:56 PM UTC

jayd16 wrote: post #111

u1hcw9nx wrote: post #85

Earlier quoted context omitted.

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Why not use something absolute, like nand-gates per volume?

I am not a chip designer, doesn't area matter way more than volume? Vertical space is basically free; it's horizontal space that is at a huge premium.

Re: IBM debuts sub-1 nanometer chip technology

#114

Post by ternaryoperator » Thu, Jun 25, 2026, 8:56 PM UTC

victor106 wrote: post #69

Keep hearing that IBM makes these incredible chips but don’t see anyone using IBM chips. What do they do with them?

Their line of POWER chips are used in their mainframes

Re: IBM debuts sub-1 nanometer chip technology

#115

Post by kitd » Thu, Jun 25, 2026, 9:00 PM UTC

perching_aix wrote: post #77

I wonder at what point does it become deceptive in the legally biting way to market process nodes like this. One can wax and wane a bunch about industry terminology status quo, but this is mental.

It'll be a brave man who takes on the IBM legal department over terminology in widespread use.

Re: IBM debuts sub-1 nanometer chip technology

#116

Post by Smalltalker-80 » Thu, Jun 25, 2026, 9:01 PM UTC

u1hcw9nx wrote: post #85

buran77 wrote: post #10

> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…

Unlike marketing terms, "nm density" is actually useful measure. It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011 and before. A "0.7 nm" node has equivalent transistor density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.

Yeah, the actual sizes are right there in the pictures, and never < 1 nm.

Re: IBM debuts sub-1 nanometer chip technology

#117

Post by quantum_state » Thu, Jun 25, 2026, 9:11 PM UTC

kailden wrote: post #72

gabrielhidasy wrote: post #67

Earlier quoted context omitted.

Just get better marketers to say your 2nm process has more gates per sqmm than your competition 1nm process.

Exactly. WatsonX AI quantum angstroms for e-business.

At some point, people would not know if they have the deal or not have the deal in this new era of quantum e-business ...

Re: IBM debuts sub-1 nanometer chip technology

#118

Post by formerly_proven » Thu, Jun 25, 2026, 9:29 PM UTC

measurablefunc wrote: post #101

gruez wrote: post #91

Earlier quoted context omitted.

Not all densities is mass per volume. eg. population density.

It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area. > Historically, "node" sizes (like 28nm or 7nm) directly correlated to the physical length of a transistor's gate. Today, names like 3nm or 2nm reflect a marketing generation. The actual transistors are significantly larger than these nano…

> It's a physical quantity per some unit of spatial measurement so the units still don't match up b/c in one case the transistors are stacked per volume & in the other case per area.

"Planar" and "3D" in this context refers to the shape of the transistors themselves. In a planar transistor the functional structure is spread out in the area, like this: https://en.wikipedia.org/wiki/File:MOSFET_functioning_body.s... while 3D transistors spread into the volume: https://en.wikipedia.org/wiki/Multigate_device#/media/File:D...

However the active devices are still just one layer. This isn't like 3D NAND where you actually have transistors on top of each other. So the comparison only considers the area for both kinds of transistors.

Re: IBM debuts sub-1 nanometer chip technology

#119

Post by roelmore » Thu, Jun 25, 2026, 9:31 PM UTC

amelius wrote: post #96

Legend2440 wrote: post #47

Earlier quoted context omitted.

It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.

Who started it?

Smart money would be on the first person who realized that the expertise required to understand the technical details had grown beyond that possessed by 51%+ of stock investing (trading?) population as weighted by transaction volume.

Re: IBM debuts sub-1 nanometer chip technology

#120

Post by duckmysick » Thu, Jun 25, 2026, 9:31 PM UTC

wasabi991011 wrote: post #106

monirmamoun wrote: post #64

Two big problems 1) NOBODY knows what IBM's definition of "sub 1nm" means 2) IBM bullshits so much more than anyone including Intel (remember the "teleportation" ads years ago) that nobody is going to waste time researching what they mean in reality

> remember the "teleportation" ads years ago Never heard of this, care to elaborate?

I think the OP references Intel ads with Jim Parsons from like a decade ago.

https://www.youtube.com/watch?v=PQWpYQm60P4

There were more of them, including some with other celebrities.