61–70 of 217 posts
Earlier quoted context omitted.
My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?
If they're adding a dimension, the marketing should reflect that. I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
Earlier quoted context omitted.
> IBM no longer owns any fabs Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space" I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability
It's a lab. It's where ASML brings up the prototype machine and gets it working, with IBM talent working out the problems and getting it ready for commercial operation. They won't make chips at scale there: the facility isn't designed for that part. The thing to understand here is that isn't a simple, clean, comprehensible business arrangement. The Albany facility is highly subsidized by the state. IBM has their hook…
My understanding is that ASML's acquisition of Cymer in California (the actual EUV light source technology) in 2014 was only permitted under a strict technology sharing and export agreement with the US government. And that the technology development and production had to remain within the US.
The USA CHIPS Act and NY State have provided $100 billion+ in funding with the expectation that ASML's core R&D and "prototyping" like this will be done in the US in partnership with US companies (like IBM).
> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…
Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.
Why doesn't the industry use something like transistor density per cubic cm? This would extend to 3d cases and impossible to fake
One of the images has "15 rows of Si atoms". Is there a limit to how small things can go? A single atom? Is there a physical/molecular limit to Moore's Law?
Yes, and we're already there. We've been there for quite a while, in fact. Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know.…
I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.
> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible. Continuing the well establi…
As it can be seen from the photos, horizontally the features are much bigger than 5 nm. For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm. The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary. The vertical thicknesses of various layers may be of only a few nanomet…
also, I was expecting to see cfets mentioned.