Excellent. Put me down for a couple.
Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11
Aegis – open-source FPGA silicon
41–46 of 46 posts
Re: Aegis – open-source FPGA silicon
#42Excellent. Put me down for a couple.
me too please
Please vote in this poll: https://github.com/MidstallSoftware/aegis/discussions/11
Re: Aegis – open-source FPGA silicon
#43We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…
12 GHz on 180nm? Sorry, that's not possible. What's the actual clock speed?
Complex processors like AMD Athlon and Intel Pentium 4, which were made in 180 nm a quarter of century ago, had clock frequencies between 1 GHz and 2 GHz. Pentium 4 used internally a double frequency clock for the simpler 32-bit arithmetic-logic units, i.e. up to around 4 GHz.
Today the manufacturing process could be better optimized than 25 years ago, so some logic circuits much simpler than a 64-bit CPU (the previous were 32-bit CPUs for integers, but they had 64-bit/80-bit FPUs working at full speed), i.e. with much less gate delays per pipeline stage, might be able to reach 12 GHz.
However, something like a 64-bit ALU will certainly not reach 12 GHz. Even a 32-bit ALU is very unlikely to reach 12 GHz. Simple things, like shift registers and Galois-field counters, might reach such speeds, or even higher.
The next CMOS process generation, i.e. 130 nm, already allows making complex processors with more than a half of the maximum clock frequency of the fastest processors of today. It also allows making analog amplifiers and mixers for the 5 GHz WiFi frequency bands.
Re: Aegis – open-source FPGA silicon
#44Earlier quoted context omitted.
I went though the list of prices at Europractice. Waferspace is 7000 USD for 1k of 20mm2. That is a per mm2 price of 350 USD. I could not find any offering at Europrice that matches that?
Chip fabs do not publish prices. First of all, the cost price of making a wafer is not a single item. What node, on what chip machine are they going to be made, what process, what PDK, are you breaking any of the PDK limits, what testing has your design went trough, what types and numbers of slices to chip the wafer, are there test before the chips get chipped or only after they are chipped, what packages the chips a…
You are the one that claimed the prices of those shuttle services were lower than that of WaferSpace. 7k USD for 1k chips of 20mm2 at 180nm. Is it not the case?
Re: Aegis – open-source FPGA silicon
#45Earlier quoted context omitted.
Chip fabs do not publish prices. First of all, the cost price of making a wafer is not a single item. What node, on what chip machine are they going to be made, what process, what PDK, are you breaking any of the PDK limits, what testing has your design went trough, what types and numbers of slices to chip the wafer, are there test before the chips get chipped or only after they are chipped, what packages the chips a…
You are the one that claimed the prices of those shuttle services were lower than that of WaferSpace. 7k USD for 1k chips of 20mm2 at 180nm. Is it not the case?
There are over a hundred [1] shuttle services (group purchasing of test chips on a multi-project wafer) in they world. Several are even free, academic and universities offer them to students or PhD, some state sponsored in China and Europe, some start at $100, some very specialized, others as a 'sample' from big chip fabs, some offered on the cheap to get you hooked, tied in to a chip fab's PDK onder several NDA's.
[1] https://www.google.com/search?client=safari&rls=en&q=shuttle...
Re: Aegis – open-source FPGA silicon
#46Earlier quoted context omitted.
12 GHz on 180nm? Sorry, that's not possible. What's the actual clock speed?
Complex processors like AMD Athlon and Intel Pentium 4, which were made in 180 nm a quarter of century ago, had clock frequencies between 1 GHz and 2 GHz. Pentium 4 used internally a double frequency clock for the simpler 32-bit arithmetic-logic units, i.e. up to around 4 GHz. Today the manufacturing process could be better optimized than 25 years ago, so some logic circuits much simpler than a 64-bit CPU (the previo…
This is plainly wrong. I'm a chip designer. There's no way to implement a DFF operating at 12 GHz in 180nm, period. This isn't an optimization problem, it is physics.