21–30 of 46 posts
Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
[dead]
How do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
It's very common to xray the dies, especially for debugging. Also common is to etch it layer by layer, take photos and rebuild the circuit schematic, mainly for reverse engineering but I've seen companies doing it to their own dies too.
Things get more blurry at the board level, the combinations of suppliers and service providers are endless.
We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…
Earlier quoted context omitted.
How do you verify that the fab produces the design authentically? They could create a security vulnerability only they know how to exploit.
Because you can just look into it and see if it's what you sent fof production, and if not and the word gets out you are done as a fab. Fab business is about trust. You also should trust that your design isn't leaked to the competition. It's very common to xray the dies, especially for debugging. Also common is to etch it layer by layer, take photos and rebuild the circuit schematic, mainly for reverse engineering bu…
Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
Earlier quoted context omitted.
Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
What are your thoughts on including a RISC-V hardcore along with the gates? Because for almost all projects I can imagine using FPGA for, I would want a microcontroller also. This might however be slightly colored by me being a software/firmware first type of electronics engineer. Thinking especially for the smaller gate counts, like under 10k - because there a soft CPU takes up very precious resources.
We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…
12 GHz on 180nm? Sorry, that's not possible. What's the actual clock speed?
At 110nm I measured when a transistor was switching the second transistor on its output. I can prove it, can you disprove it?
A consistent 12Ghz signal cascade was (repeatedly) tested and confirmed on a 28nm asynchronous chip [1].
Why would it be impossible? [2].
We measure 800 Ghz and teraherz clocks on niobium superconducting Josephson Junctions [3,4,5].
[1] https://byrdsight.com/asynchronous-technology-has-its-time-f... ( See also on the slides in the video talk)
[2] "If an elderly but distinguished scientist says that something is possible, he is almost certainly right; but if he says that it is impossible, he is very probably wrong." - Arthur C. Clarke
[3] Ivan Sutherland Keynote Single Flux Quantum SFQ Ditigal Electronics Digital circuits totally distinct from Quan https://www.youtube.com/watch?v=KMVV3ErGSVY
[4] https://www.researchgate.net/profile/Jerome-Pety/publication...
[5] https://scholar.google.com/scholar?hl=en&as_sdt=0,5&qsp=3&q=...
Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…