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Aegis – open-source FPGA silicon

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Re: Aegis – open-source FPGA silicon

#31

Post by morphle »

Neywiny wrote: post #29
morphle wrote: post #12

We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…

VU19P = 3M gates how? It has more than 3M LUTs and each LUT is certainly > 1 gate

I guess the AMD Versal Premium VP1902 adaptive SoC has 18.5 million cells. The VU19P is more than half in LUT count.

Morphle Logic WSI has over 47,169,811 yellow cells. You could say that a single yellow Morphle Logic cell is more complex than ten Versal cells, but it's an apples and oranges comparison. However you count it, the $500 Morphle Logic WSI (cost price) has 10 billion transistors, the AMD Versal Premium cost over $100.000 and is effectively smaller in terms of gates, LUTs or cells even though it has 138 billion transistors.

If I made the Morphle Logic WSI in 2nm TSMC, it would have more than 52 trillion transistors [1], at least 245,283,018,867 yellow cells and cost over $22.500. You could easily emulate several AMD Versal Premium VP1902 FPGA's on the wafer.

[1] https://www.youtube.com/watch?v=vbqKClBwFwI

Re: Aegis – open-source FPGA silicon

#32

Post by Neywiny »

morphle wrote: post #31
Neywiny wrote: post #29

Earlier quoted context omitted.

VU19P = 3M gates how? It has more than 3M LUTs and each LUT is certainly > 1 gate

I guess the AMD Versal Premium VP1902 adaptive SoC has 18.5 million cells. The VU19P is more than half in LUT count. Morphle Logic WSI has over 47,169,811 yellow cells. You could say that a single yellow Morphle Logic cell is more complex than ten Versal cells, but it's an apples and oranges comparison. However you count it, the $500 Morphle Logic WSI (cost price) has 10 billion transistors, the AMD Versal Premium co…

Tbh I did forget about versal but yes the PL of the VP1902 absolutely has more than 3 million logic gates no matter how you slice it. I have no doubt that there are non-fpgas with more, but it is a bit disingenuos to say they're orders of magnitude under where they actually are.

I'll also note that it has a ton of SRAM onboard which doesn't shrink well, so I'm not convinced just by that extrapolation that you could eclipse it with a simple lithography shrink. Unless you really meant several per wafer, which doesn't really feel like a hard target...

Re: Aegis – open-source FPGA silicon

#33

Post by infinitewars »

This is quite a milestone for open silicon. Having a completely auditable path from RTL down to GDS targeting the GF180MCU via wafer.space is no small feat-especially pulling it all together with a Nix-integrated toolchain and Dart for the hardware generation.

On the I/O side, getting even a basic 400MHz oversampled SerDes into a first-gen test chip puts this way ahead of most academic open FPGA efforts.

Really looking forward to seeing the Terra family expand and how the test chips perform.

Re: Aegis – open-source FPGA silicon

#34

Post by Bluebirt »

morphle wrote: post #27
bgnn wrote: post #23

Earlier quoted context omitted.

12 GHz on 180nm? Sorry, that's not possible. What's the actual clock speed?

Morphle Logic is asynchronous logic so there is no clock. At 110nm I measured when a transistor was switching the second transistor on its output. I can prove it, can you disprove it? A consistent 12Ghz signal cascade was (repeatedly) tested and confirmed on a 28nm asynchronous chip [1]. Why would it be impossible? [2]. We measure 800 Ghz and teraherz clocks on niobium superconducting Josephson Junctions [3,4,5]. [1]…

You must be fun at parties...

Re: Aegis – open-source FPGA silicon

#35

Post by bajsejohannes »

morphle wrote: post #12

We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…

Interesting to see an alternative approach.

I struggled a bit to understand the explanation on github, but eventually got to something that made sense. It would have helped me if it said up front that

- 0, 1, N and Y pass the input signal on (works like a | or - in the input direction), and that - when a circuit has both a 0 and 1 output value, the output becomes 0 (which is why 11 is an AND and not a OR)

Hopefully that's correctly understood? If so, maybe consider updating the explanation for the next person.

Also, a question: Does a 0 and 1 on the same circuit consume more power than two 0s or two 1s due to the conflicting values? Or is it solved with transistors at the cost of propagation delay? Or something else?

Re: Aegis – open-source FPGA silicon

#36

Post by fiberhood »

bajsejohannes wrote: post #35
morphle wrote: post #12

We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M... The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips. In the case of Morphle Logic we make wafer scale…

Interesting to see an alternative approach. I struggled a bit to understand the explanation on github, but eventually got to something that made sense. It would have helped me if it said up front that - 0, 1, N and Y pass the input signal on (works like a | or - in the input direction), and that - when a circuit has both a 0 and 1 output value, the output becomes 0 (which is why 11 is an AND and not a OR) Hopefully t…

Thank you for pointing out I need to improve the explanations.

We made seven different implementations of Morphle Logic, some of which are lower power, use less transistors, different ways to do asynchronous logic or are based on superconducting josephson junctions instead of transistors.

In this particular case the two tokens probably consume the same amount of power regardless of their value, but only measurements will tell.

Re: Aegis – open-source FPGA silicon

#37

Post by jononor »

morphle wrote: post #28
jononor wrote: post #18

Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.

1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.

Interesting! Which EDA tool must I use for those, and what is the price of that? Will these services accept a single run of 1k?

Re: Aegis – open-source FPGA silicon

#38

Post by jononor »

morphle wrote: post #28
jononor wrote: post #18

Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.

1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.

I went though the list of prices at Europractice. Waferspace is 7000 USD for 1k of 20mm2. That is a per mm2 price of 350 USD. I could not find any offering at Europrice that matches that?

Re: Aegis – open-source FPGA silicon

#39

Post by morphle »

jononor wrote: post #38
morphle wrote: post #28

Earlier quoted context omitted.

1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.

I went though the list of prices at Europractice. Waferspace is 7000 USD for 1k of 20mm2. That is a per mm2 price of 350 USD. I could not find any offering at Europrice that matches that?

Chip fabs do not publish prices. First of all, the cost price of making a wafer is not a single item. What node, on what chip machine are they going to be made, what process, what PDK, are you breaking any of the PDK limits, what testing has your design went trough, what types and numbers of slices to chip the wafer, are there test before the chips get chipped or only after they are chipped, what packages the chips are in. Insurance types and fees, locations, what batches. All these steps can be performed in different fabs with different companies and subcontractors, between them they might have to ship your wafer under clean room conditions, sometimes flow around the world. A wafer batch price is a very complex multi-party negotiation under NDAs, none of them has ever been made public. Show me any credible price quotes from the last 55 year (fe few million chips). You can't.

On these multi party shuttle projects this gets simplified into a price list where they quote you a high ball-park number that covers your test chips cost by a wide margin. The actual cost is never disclosed, certainly not on price lists.

A mask set maker and a chip fab create half of your product, they own that intellectual product and they won't even tell you what it has cost them. They merge their product with yours, now thyey co-own your product. There are only a few competing companies world wide (and getting fewer every year) and they compete on all this non-disclosed stuff. Prices above all. Never belief what you read on the internet, especially in the chips war industry.

Re: Aegis – open-source FPGA silicon

#40

Post by morphle »

jononor wrote: post #37
morphle wrote: post #28

Earlier quoted context omitted.

1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.

Interesting! Which EDA tool must I use for those, and what is the price of that? Will these services accept a single run of 1k?

There are a few EDA companies, all with ancient software tools but kept up to date with the changing parameters and algorithms. You use the tools the insurance companies tell you or the mandatory tools of your chip fab suppliers. They use a lot of software tools on your design files you never get to see.

If you want to make better chips, like the low power Apple Silicon for example, you create your own EDA software tools to make the innovation. Creating a new transistor like the CFET [1] means writing new physics simulation tools, for example.

The outdated 1990's and buggy Open Lane software for example limits what kind of RAM transistors you can make or the complexity of your design.

My team makes asynchronous chips, free space optics photonics, ultra dense 2 transistor SRAM, niobium SQF chips, wafer scale integrations. All require bespoke software simulation tools, netlist rewriting tools, cross-reticle stepper exposure software (a software change in a $400 million dollar machine), etc etc. Making hardware near atomic size structures is mostly a software job. Hardware is software crystalized early, Alan Kay quips.

[1] https://www.imec-int.com/en/articles/imec-puts-complementary...

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