RISC-V Is Sloooow • Hacker News Board

Re: RISC-V Is Sloooow

#31

Post by menaerus » Tue, Mar 10, 2026, 9:06 PM UTC

patchnull wrote: post #17

menaerus wrote: post #8

Earlier quoted context omitted.

Which risc-v implementation is considered fast?

[flagged]

I remember taking down some notes wrt SiFive P870 specs, comparing them to x86_64, and reaching the same conclusion. Narrower core width (4-wide vs 8-wide), lower clock frequency (peaks at 3GHz) and no turbo (?), limited support for vector execution (128-bit vs 512-bit), limited L1 bandwidth (1x 128-bit load/cycle?), limited FP compute (2x 128-bit vs 2x 512-bit), load queue is also inconveniently small with 48 entries (affecting already limited load bandwidth), unclear system memory bandwidth and how it scales wrt the number of cores (L3 contention) although for the latter they seem to use what AMD is doing (exclusive L3 cache per chiplet).

Re: RISC-V Is Sloooow

#32

Post by sofixa » Tue, Mar 10, 2026, 9:06 PM UTC

IshKebab wrote: post #14

leni536 wrote: post #9

Is cross compilation out of the question?

It's usually an enormous pain to set up. QEMU is probably the best option.

Depends on the language, it's pretty trivial with Go.

Re: RISC-V Is Sloooow

#33

Post by andrepd » Tue, Mar 10, 2026, 9:08 PM UTC

There's zero mention of hardware specs or cost beyond architecture and core counts... What is the purpose of this post?

Anyway, it's hardly surprising that a young ISA with not a 1/1000th of the investment of x86 or ARM has slower chips than them x)

Re: RISC-V Is Sloooow

#34

Post by rwmj » Tue, Mar 10, 2026, 9:09 PM UTC

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

Marcin is working with us on RISC-V enablement for Fedora and RHEL, he's well aware of the problem with current implementations. We're hopeful that this'll be pretty much resolved by the end of the year.

Re: RISC-V Is Sloooow

#35

Post by NooneAtAll3 » Tue, Mar 10, 2026, 9:10 PM UTC

menaerus wrote: post #8

rbanffy wrote: post #4

Earlier quoted context omitted.

I did read it. A Banana Pi is not the fastest developer platform. The title is misleading. BTW, it's quite impressive how the s390x is so fast per core compared to the others. I mean, of course it's fast - we all knew that. And don't let IBM legal see this can be considered a published benchmark, because they are very shy about s390x performance numbers.

Which risc-v implementation is considered fast?

DC-ROMA 2 is on the Rasperry 4 level of performance last I heard

Re: RISC-V Is Sloooow

#36

Post by Aurornis » Tue, Mar 10, 2026, 9:11 PM UTC

rbanffy wrote: post #4

dmitrygr wrote: post #3

Earlier quoted context omitted.

IF you care to read the article, they indeed do not blame the architecture but the available silicon implementations.

I did read it. A Banana Pi is not the fastest developer platform. The title is misleading. BTW, it's quite impressive how the s390x is so fast per core compared to the others. I mean, of course it's fast - we all knew that. And don't let IBM legal see this can be considered a published benchmark, because they are very shy about s390x performance numbers.

> A Banana Pi is not the fastest developer platform.

What is the current fastest platform that isn’t exorbitantly expensive? Not upcoming releases, but something I can actually buy.

I check in every 3-6 months but the situation hasn’t changed significantly yet.

Re: RISC-V Is Sloooow

#37

Post by unethical_ban » Tue, Mar 10, 2026, 9:13 PM UTC

jnovek wrote: post #20

api wrote: post #12

Earlier quoted context omitted.

A pattern I've noticed for a very long time: A lot of times the path to the highest performing CPU seems to be to optimize for power first , then speed, then repeat. That's because power and heat are a major design constraint that limits speed. I first noticed this way back with the Pentium 4 "Netburst" architecture vs. the smaller x86 cores that became the ancestor of the Core architecture. Intel eventually ran into…

I don’t have a micro architecture background so I apologize if this is obvious — What do power and speed mean in this context?

One could say "Optimize for efficiency first, then performance".

Re: RISC-V Is Sloooow

#38

Post by cogman10 » Tue, Mar 10, 2026, 9:14 PM UTC

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

> AND the software with no architecture-specific optimisations

The optimizations that'd be applied to ARM and MIPS would be equally applicable to RISC-V. I do not believe this is a lack of software optimization issue.

We are well past the days where hand written assembly gives much benefit, and modern compilers like gcc and llvm do nearly identical work right up until it comes to instruction emissions (including determining where SIMD instructions could be placed).

Unless these chips have very very weird performance characteristics (like the weirdness around x86's lea instruction being used for arithmetic) there's just not going to be a lot of missed heuristics.

Re: RISC-V Is Sloooow

#39

Post by genxy » Tue, Mar 10, 2026, 9:15 PM UTC

mananaysiempre wrote: post #24

balou23 wrote: post #18

Earlier quoted context omitted.

TBH I still don't really get how it's different from MIPS. As far as I can tell... Loongson seems to be really just MIPS, while LoongArch is MIPS with some extra instructions.

But legally distinct! I guess calling it Ｍ○ＰＳ was not enough for plausible deniability.

ISAs shouldn't be patentable in the first place.

Re: RISC-V Is Sloooow

#40

Post by fidotron » Tue, Mar 10, 2026, 9:15 PM UTC

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

> RISC-V will get there, eventually.

Not trolling: I legitimately don't see why this is assumed to be true. It is one of those things that is true only once it has been achieved. Otherwise we would be able to create super high performance Sparc or SuperH processors, and we don't.

As you note, Arm once was fast, then slow, then fast. RISC-V has never actually been fast. It has enabled surprisingly good implementations by small numbers of people, but competing at the high end (mobile, desktop or server) it is not.