RISC-V Is Sloooow • Hacker News Board

Re: RISC-V Is Sloooow

#11

Post by spiderice » Tue, Mar 10, 2026, 8:35 PM UTC

dmitrygr wrote: post #3

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

IF you care to read the article, they indeed do not blame the architecture but the available silicon implementations.

Then how do you justify the title?

Re: RISC-V Is Sloooow

#12

Post by api » Tue, Mar 10, 2026, 8:38 PM UTC

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

A pattern I've noticed for a very long time:

A lot of times the path to the highest performing CPU seems to be to optimize for power first, then speed, then repeat. That's because power and heat are a major design constraint that limits speed.

I first noticed this way back with the Pentium 4 "Netburst" architecture vs. the smaller x86 cores that became the ancestor of the Core architecture. Intel eventually ran into a wall with P4 and then branched high performance cores off those lower-power ones and that's what gave us the venerable Core architecture that made Intel the dominant CPU maker for over a decade.

ARM's history is another example.

Re: RISC-V Is Sloooow

#13

Post by lifis » Tue, Mar 10, 2026, 8:38 PM UTC

Or they could fix cross compilation and then compile it on a normal x86_64 server

Re: RISC-V Is Sloooow

#14

Post by IshKebab » Tue, Mar 10, 2026, 8:39 PM UTC

leni536 wrote: post #9

Is cross compilation out of the question?

It's usually an enormous pain to set up. QEMU is probably the best option.

Re: RISC-V Is Sloooow

#15

Post by IshKebab » Tue, Mar 10, 2026, 8:41 PM UTC

Yeah it's a few years behind ARM, but not that many. Imagine trying to compile this on ARM 10 years ago. It would be similarly painful.

Re: RISC-V Is Sloooow

#16

Post by rbalint » Tue, Mar 10, 2026, 8:46 PM UTC

If the builds are slow, build accelerators can help a lot. Ccache would work for sure and there is also firebuild, that can accelerate the linker phase and many other tools in builds.

Re: RISC-V Is Sloooow

#17

Post by patchnull » Tue, Mar 10, 2026, 8:48 PM UTC

menaerus wrote: post #8

rbanffy wrote: post #4

Earlier quoted context omitted.

I did read it. A Banana Pi is not the fastest developer platform. The title is misleading. BTW, it's quite impressive how the s390x is so fast per core compared to the others. I mean, of course it's fast - we all knew that. And don't let IBM legal see this can be considered a published benchmark, because they are very shy about s390x performance numbers.

Which risc-v implementation is considered fast?

[flagged]

Re: RISC-V Is Sloooow

#18

Post by balou23 » Tue, Mar 10, 2026, 8:48 PM UTC

rbanffy wrote: post #7

topspin wrote: post #6

Earlier quoted context omitted.

I keep checking in on Tenstorrent every few months thinking Keller is going to rock our world... losing hope. At this point the most likely place for truly competitive RISC-V to appear is China.

> At this point the most likely place for fast RISC-V to appear is China. Or we just adopt Loongson.

TBH I still don't really get how it's different from MIPS. As far as I can tell... Loongson seems to be really just MIPS, while LoongArch is MIPS with some extra instructions.

Re: RISC-V Is Sloooow

#19

Post by brcmthrowaway » Tue, Mar 10, 2026, 8:50 PM UTC

Why is it slow? I thought we have Rivos chips

Re: RISC-V Is Sloooow

#20

Post by jnovek » Tue, Mar 10, 2026, 8:51 PM UTC

api wrote: post #12

rbanffy wrote: post #2

Don't blame the ISA - blame the silicon implementations AND the software with no architecture-specific optimisations. RISC-V will get there, eventually. I remember that ARM started as a speed demon with conscious power consumption, then was surpassed by x86s and PPCs on desktops and moved to embedded, where it shone by being very frugal with power, only to now be leaving the embedded space with implementations optimi…

A pattern I've noticed for a very long time: A lot of times the path to the highest performing CPU seems to be to optimize for power first , then speed, then repeat. That's because power and heat are a major design constraint that limits speed. I first noticed this way back with the Pentium 4 "Netburst" architecture vs. the smaller x86 cores that became the ancestor of the Core architecture. Intel eventually ran into…

I don’t have a micro architecture background so I apologize if this is obvious — What do power and speed mean in this context?