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RISC-V Is Sloooow

marcin.juszkiewicz.com.pl

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Re: RISC-V Is Sloooow

#21

Post by rbanffy »

gt0 wrote: post #10
rbanffy wrote: post #4

Earlier quoted context omitted.

I did read it. A Banana Pi is not the fastest developer platform. The title is misleading. BTW, it's quite impressive how the s390x is so fast per core compared to the others. I mean, of course it's fast - we all knew that. And don't let IBM legal see this can be considered a published benchmark, because they are very shy about s390x performance numbers.

I was really surprised by the s390x performance, but I also don't really understand why there are build time listed by architecture, not the actual processors.

Probably because that's just the infrastructure they have.

Re: RISC-V Is Sloooow

#22

Post by Joel_Mckay »

Any new hardware lags in compiler optimizations.

i. llvm presentation can thrash caches if setup wrong (given the plethora of RISC-V fragmented versions, most compilers won't cover every vanity silicon.)

ii. gcc is also "slow" in general, but is predictable/reliable

iii. emulation is always slower than kvm in qemu

It may seem silly, but I'd try a gcc build with -O0 flag, and a toy unit test with -S to see if the ASM is actually foobar. One may have to force the -mtune=boom flag to narrow your search. Best regards =3

Re: RISC-V Is Sloooow

#23

Post by Levitating »

This is why felix has been building the risc-v archlinux repositories[1] using the Milk-V Pioneer.

I think the ban of SOPHGO is part to blame for the slow development.[2] They had the most performant and interesting SOCs. I had a bunch of pre-orders for the Milk-V Oasis before it was cancelled. It was supposed to come out a while ago, using the SG2380, supposedly much more performant than the Milk-V Titan mentioned in the article (which still isn't out).

It was also SOPHGO's SOCs that powered the crazy cheap/performant/versatile Milk-V DUO boards. They have the ability to switch ARM/RISC-V architecture.

[1]: https://archriscv.felixc.at/

[2]: https://www.tomshardware.com/tech-industry/artificial-intell...

Re: RISC-V Is Sloooow

#24

Post by mananaysiempre »

balou23 wrote: post #18
rbanffy wrote: post #7

Earlier quoted context omitted.

> At this point the most likely place for fast RISC-V to appear is China. Or we just adopt Loongson.

TBH I still don't really get how it's different from MIPS. As far as I can tell... Loongson seems to be really just MIPS, while LoongArch is MIPS with some extra instructions.

But legally distinct! I guess calling it Ｍ○ＰＳ was not enough for plausible deniability.

Re: RISC-V Is Sloooow

#27

Post by primis »

throwaway27448 wrote: post #25

[flagged]

Hey! I get this is a throwaway account so you might not answer, but I really, really don't like opening an article and having the first thing I see in a thread be someone calling the author a slur. There are ways of expressing insult without bringing intellectual disabilities into the mix.

Re: RISC-V Is Sloooow

#28

Post by hackerInnen »

IshKebab wrote: post #15

Yeah it's a few years behind ARM, but not that many. Imagine trying to compile this on ARM 10 years ago. It would be similarly painful.

This. While I doubt that there will be a good (whatever that means) desktop risc-v CPU anytime soon, I do think that it will eventually catch up in embedded systems and special applications. Maybe even high core count servers.

It just takes time, people who believe in it and tons of money. Will see where the journey goes, but I am a big risc-v believer

Re: RISC-V Is Sloooow

#29

Post by McP »

jnovek wrote: post #20
api wrote: post #12

Earlier quoted context omitted.

A pattern I've noticed for a very long time: A lot of times the path to the highest performing CPU seems to be to optimize for power first , then speed, then repeat. That's because power and heat are a major design constraint that limits speed. I first noticed this way back with the Pentium 4 "Netburst" architecture vs. the smaller x86 cores that became the ancestor of the Core architecture. Intel eventually ran into…

I don’t have a micro architecture background so I apologize if this is obvious — What do power and speed mean in this context?

Power - how many Watts does it need? Speed - how quickly can it perform operations?

Re: RISC-V Is Sloooow

#30

Post by dmit »

primis wrote: post #27
throwaway27448 wrote: post #25

[flagged]

Hey! I get this is a throwaway account so you might not answer, but I really, really don't like opening an article and having the first thing I see in a thread be someone calling the author a slur. There are ways of expressing insult without bringing intellectual disabilities into the mix.

For future readers: throwaway27448's comment used to say something completely different, featuring the r-slur, and then immediately edited.
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