LinkedIn tells me: https://uk.linkedin.com/in/ttchisholm FPGA engineer with a focus on ultra-low latency networking at Jane Street. Yikes.
Not sure i get the implication, something wrong with the company?
Designing a Low Latency 10G Ethernet Core (2023)
11–20 of 83 posts
Re: Designing a Low Latency 10G Ethernet Core (2023)
#12Earlier quoted context omitted.
On the other hand, no nights or weekends.
This is becoming less and less true every day. 24/7 markets are coming whether you want them or not, and if you're not trading outside of US Equity hours you're leaving significant money on the table.
> This is becoming less and less true every day. 24/7 markets are coming whether you want them or not
This has still to exist for real. Every couple of years there is a resurgence of "we should have 24/7 equity markets", followed by milestone announcements of Nasdaq.
The reality is more... nuanced.
First, there has to be a wide enough window for corporate actions and news dissemination to happen. Not only is that a regulatory requirement, but anyway no sane investor would like to trade in such a window even if possible.
Second, there are already early sessions, pre opening sessions, and late sessions on most American markets. The liquidity there is almost inexistant, so I wouldn't say there is a huge demand for extended trading hours by non-retail participants.
And last, half the liquidity of US markets is not on lit books, and half the remaining lit liquidity is close to the auction. I don't think it would even be a net profit for lit exchanges to extend their hours in these conditions. As for dark pool, I think only 2 or 3 of the smaller ones are 24/7, like the one from IB.
> if you're not trading outside of US Equity hours you're leaving significant money on the table
HFTs need a lot of liquidity and tight spreads, that's pretty much only doable at scale in the US and Japan. Europe and EM are either not liquid enough, or only really able to sustain low capital ad-hoc strategies.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#13It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
I'd want to know why they had such a system as a single point of failure
Re: Designing a Low Latency 10G Ethernet Core (2023)
#14less than 60ns loopback latency There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
The other funny bit is that one-way PCIe latency is 250ns-ish (don't quote me on the exact numbers), which imposes a hard 1us constraint on latency between two hosts.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#15less than 60ns loopback latency There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
Cut Through switching needs what, 14 bytes? Thats ~12ns on 10G? How would you do it in 40 cycles?
Re: Designing a Low Latency 10G Ethernet Core (2023)
#16less than 60ns loopback latency There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
Cut Through switching needs what, 14 bytes? Thats ~12ns on 10G? How would you do it in 40 cycles?
Not my are of expertise, but afaik the neat part is that you don't do it in cycles. The "program" lives as the transistor layout, not as instructions
Re: Designing a Low Latency 10G Ethernet Core (2023)
#17Earlier quoted context omitted.
Cut Through switching needs what, 14 bytes? Thats ~12ns on 10G? How would you do it in 40 cycles?
Not my are of expertise, but afaik the neat part is that you don't do it in cycles. The "program" lives as the transistor layout, not as instructions
The cycles in question are not those of any processor, but those of the signal coming in the wire. No matter how it's implemented, a switch cannot react to bits that are still in the wire and haven't made it to the switch yet.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#18LinkedIn tells me: https://uk.linkedin.com/in/ttchisholm FPGA engineer with a focus on ultra-low latency networking at Jane Street. Yikes.
Is this really unexpected? A person who knows ultra-low-latency networking with FPGAs writes an article about making low-latency networking hardware for a company that needs high-speed, low-latency communications (high-frequency trading)
Re: Designing a Low Latency 10G Ethernet Core (2023)
#19LinkedIn tells me: https://uk.linkedin.com/in/ttchisholm FPGA engineer with a focus on ultra-low latency networking at Jane Street. Yikes.
Not sure i get the implication, something wrong with the company?
Some people just love dropping “yikes” type comments and then never explaining themselves.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#20less than 60ns loopback latency There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
Cut Through switching needs what, 14 bytes? Thats ~12ns on 10G? How would you do it in 40 cycles?
why do you assume the full ethernet header?
IIRC. cut-through only needs the first 6 bytes. Since it only needs the destination address for the port lookup.
Potentially the first bit, on broadcast.