Designing a Low Latency 10G Ethernet Core (2023)
ttchisholm.github.io
Designing a Low Latency 10G Ethernet Core (2023)
1–10 of 83 posts
Re: Designing a Low Latency 10G Ethernet Core (2023)
#2It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot
Re: Designing a Low Latency 10G Ethernet Core (2023)
#3It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot
I feel like it's also got to be super stressful
Imagine getting a call you system is down and is costing them millions per hour
Re: Designing a Low Latency 10G Ethernet Core (2023)
#4It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
On the other hand, no nights or weekends.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#5Re: Designing a Low Latency 10G Ethernet Core (2023)
#6Earlier quoted context omitted.
I feel like it's also got to be super stressful Imagine getting a call you system is down and is costing them millions per hour
On the other hand, no nights or weekends.
This is becoming less and less true every day. 24/7 markets are coming whether you want them or not, and if you're not trading outside of US Equity hours you're leaving significant money on the table.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#7Earlier quoted context omitted.
On the other hand, no nights or weekends.
This is becoming less and less true every day. 24/7 markets are coming whether you want them or not, and if you're not trading outside of US Equity hours you're leaving significant money on the table.
Genuinely curious - would 24x7 low-latency trading matter then? Wouldn't after-hours trading (for your local timezone) be happening on an exchange in another location?
Or do you mean dark pools/private exchanges that may run 24x7?
Re: Designing a Low Latency 10G Ethernet Core (2023)
#8It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot
I agree! Seems like very interesting work.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#9less than 60ns loopback latency
There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.
Re: Designing a Low Latency 10G Ethernet Core (2023)
#10LinkedIn tells me: https://uk.linkedin.com/in/ttchisholm
FPGA engineer with a focus on ultra-low latency networking at Jane Street.