While an interesting read, the title is a bit misleading since I didn’t see any actual “test results” in the post.
They are linked at the bottom of Mr. Fog's post. For example on page 142 of this:
Test Results for AMD Zen 5
11–20 of 80 posts
Re: Test Results for AMD Zen 5
#12Vector ALU instruction latencies are understandably listed as 2 and higher, but this is not strictly the case. From AMD's Zen 5 optimization manual [1], we have
The floating point schedulers have a slow region, in the oldest entries of a scheduler and only when the scheduler is full. If an operation is in the slow region and it is dependent on a 1-cycle latency operation, it will see a 1 cycle latency penalty.
There is no penalty for operations in the slow region that depend on longer latency operations or loads.
There is no penalty for any operations in the fast region.
To write a latency test that does not see this penalty, the test needs to keep the FP schedulers from filling up.
The latency test could interleave NOPs to prevent the scheduler from filling up.
[1] https://www.amd.com/content/dam/amd/en/documents/processor-t...
Re: Test Results for AMD Zen 5
#13Re: Test Results for AMD Zen 5
#14> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…
Cache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures.
Re: Test Results for AMD Zen 5
#15> Integer vector instructions and floating point vector instructions now have the same latencies.
There is very little reason to use integers for anything anymore. Loop counter? Why not make it a double - you never know when you might need an extra 0.5 loops at the end!
Re: Test Results for AMD Zen 5
#16> Integer vector instructions and floating point vector instructions now have the same latencies. There is very little reason to use integers for anything anymore. Loop counter? Why not make it a double - you never know when you might need an extra 0.5 loops at the end!
Finally we can implement BiCGStab intuitively!
Re: Test Results for AMD Zen 5
#17> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…
Cache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures.
"Network on Chip" okay got it.
Re: Test Results for AMD Zen 5
#18Is it better than M4?
If a laptop will need to be plugged in to deliver full performance, whilst blasting fans at full throttle, what is the point? (apart from server / workstation use, where you don't like MacOS or need different OS)
Re: Test Results for AMD Zen 5
#19> Integer vector instructions and floating point vector instructions now have the same latencies. There is very little reason to use integers for anything anymore. Loop counter? Why not make it a double - you never know when you might need an extra 0.5 loops at the end!
Integers aren't for performance. They're for precision (anything financial for example) and occasionally size.
Re: Test Results for AMD Zen 5
#20> Integer vector instructions and floating point vector instructions now have the same latencies. There is very little reason to use integers for anything anymore. Loop counter? Why not make it a double - you never know when you might need an extra 0.5 loops at the end!
Totally. Can’t wait to access the 18463.637th record in my database plus or minus a record or thousand.