Test Results for AMD Zen 5
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Test Results for AMD Zen 5
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Re: Test Results for AMD Zen 5
#2This reminds me: has anyone ever figured out why Zen 3 was missing memory renaming, but it came back in Zen 4 and Zen 5?
Re: Test Results for AMD Zen 5
#3While an interesting read, the title is a bit misleading since I didn’t see any actual “test results” in the post.
Re: Test Results for AMD Zen 5
#4While an interesting read, the title is a bit misleading since I didn’t see any actual “test results” in the post.
The detailed results are in the links at the bottom of the post.
Re: Test Results for AMD Zen 5
#5> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes.
That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads.
Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI.
AMD's website claims Zen5 is the "Leading CPU for AI" (https://www.amd.com/en/products/processors/server/epyc/ai.ht...>), but I strongly doubt that. First, they compare Zen5 (9965), which is still largely unavailable, to Xeon2 (8280), a 2 generations older processor. Xeon4 is abundantly available and comes with AMX, an exclusive feature to Intel. I doubt AVX-512 support with a 512-bit physical path and even twice as many cores will be enough to compete with that (if we consider just the ALU throughput rather than the overall system & memory).
Re: Test Results for AMD Zen 5
#6While an interesting read, the title is a bit misleading since I didn’t see any actual “test results” in the post.
AMD’s documentation for the CPU may or may not state such things as “There are six integer ALUs, four address generation units, three branch units, four vector ALUs, and two vector read/write units”, but even if it does, Agnes Fog runs actual code to check that, and often discovers corner cases that the official documentation doesn’t mention.
So, he black box tests the CPU to try and discover its innards.
Re: Test Results for AMD Zen 5
#7> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…
Well, when you consider that AVX 512 instructions have 2 or 3 reads per 1 write, there's a degree of sense here.
Consider the standard matrix multiplication primitive the FMAC / multiply and accumulate: 3 reads and one write if I'm counting correctly .... (Output = A * B + C, three reads one output).
Re: Test Results for AMD Zen 5
#8> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…
It may be easier for the memory controller to schedule two narrower writes than waiting for one 512-bit block or perhaps they just didn't substantially update the memory controller and so it still has to operate as it did in Zen 4.
Re: Test Results for AMD Zen 5
#9While an interesting read, the title is a bit misleading since I didn’t see any actual “test results” in the post.
AMD’s documentation for the CPU may or may not state such things as “There are six integer ALUs, four address generation units, three branch units, four vector ALUs, and two vector read/write units”, but even if it does, Agnes Fog runs actual code to check that, and often discovers corner cases that the official documentation doesn’t mention. So, he black box tests the CPU to try and discover its innards.
> Agnes Fog
Agner
Re: Test Results for AMD Zen 5
#10This reminds me: has anyone ever figured out why Zen 3 was missing memory renaming, but it came back in Zen 4 and Zen 5?
AMD had two leapfrogging CPU design teams. Memory renaming was added by the team that did Zen2, presumably the Zen3 team couldn't import it in time for some reason.