for those who are in the industry, it's just a marketing term.
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TSMC 2nm Process Disclosure – How Does It Measure Up?
71–80 of 106 posts
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#72Why are American fabs built in Arizona? What's so special about AZ?
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#73Why are American fabs built in Arizona? What's so special about AZ?
I suspect it's, in part, because humidity is low. The fab needs to tightly control humidity and temperature. Pulling water from air is energy intensive. Facilities team in the fab I used to work in said their most energy intensive days where the most humid days.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#74Why are American fabs built in Arizona? What's so special about AZ?
Motorola put a bunch of their early semiconductor facilities there in the 1950s so there has been a long history of the industry there along with relevant suppliers and trained work force. Microchip Technology, Amkor, Intel, First Solar continued the trend in the 70s/80s so there's a lot of related industry built up over the decades.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#75Earlier quoted context omitted.
This. The IP they need, specifically the SerDes, isn't available for 3nm (n3e) yet. That stuff isn't required for consumer devices, it comes later.
I'm not familiar with the process enough to even know what to search here, do you have some recommended reading materials about how IP becomes available for different processes and what the engineering difficulties / process is, especially for different types of IP?
I'm sorry I don't have that. It's partly supply and demand and looking at what the early adopters (Apple, these days) need. And then there's interplay with specs and related roadmaps (i.e. nobody develops their HBM PHY IP until the spec is mature enough). HPC traditionally requires specialist memory IP (e.g. CAM) and more SRAM varieties, so that comes later. Serdes also comes later since it pushes the process limits, both analogue and digital, and also is tied into ethernet standards. You might find public marketing material from Synopsys/Cadence?
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#76Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.
Doesn't Apple pay for exclusive access to N, and N+1 nodes ... shutting everyone else out from using newer node sizes.
That’s my understanding, more or less. It’s not like Apple pays to have capacity sitting idle, they just outbid everyone else to buy (and use) 100% of capacity.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#77Earlier quoted context omitted.
Doesn't Apple pay for exclusive access to N, and N+1 nodes ... shutting everyone else out from using newer node sizes.
That’s my understanding, more or less. It’s not like Apple pays to have capacity sitting idle, they just outbid everyone else to buy (and use) 100% of capacity.
I believe Apple also gives/pays TSMC for the capital needed to even do the R&D to shrink the nodes in the first place.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#78Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.
N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…
Surely you don't believe that large chips like Apple's M3 Max and M4 Max shipped while yields were still immature. So do you think that the wafers per month that TSMC is now cranking out over a year after N3B chips started landing in consumers hands still don't qualify as "full production"? How many fabs need to be fully devoted to 3nm before it is enough volume for you to consider it "full production"?
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#79Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.
N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…
I think yields is the main reason, although I'm not an expert in that area. If its a standard deviation difference than it will increase their manufacturing costs. Nvidia got around this from Ada--> Blackwell by simply increasing TDP for their high-end cards and adding more cores. Their is no IPC/efficiency/node improvement, if I'm not mistaken, for the first time gen-to-gen.
Re: TSMC 2nm Process Disclosure – How Does It Measure Up?
#80Why are American fabs built in Arizona? What's so special about AZ?
Tax breaks and politics. https://www.nytimes.com/2023/02/22/technology/arizona-chips-...