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TSMC 2nm Process Disclosure – How Does It Measure Up?

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Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#61

Post by duskwuff »

AnthonyMouse wrote: post #60
wuschel wrote: post #32

Earlier quoted context omitted.

What do you tbink is holding RiscV core design back? Is it the IP situation?

One of the things that could really help here is to create a license along the lines of "GPL for hardware" and then for a company like Google or Meta to release a design under it. The design wouldn't even have to be state of the art; something with performance equivalent to a ten year old x64 design would be valuable enough that people would use it for things if it was free. But the larger value is that then people c…

> a license along the lines of "GPL for hardware"

Like the CERN Open Hardware License?

https://cern-ohl.web.cern.ch/

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#62

Post by WhitneyLand »

ajross wrote: post #29
zozbot234 wrote: post #28

Earlier quoted context omitted.

That's not what they're saying - they say it's been a trend over the past several years. VLSI scaling is still continuing, and the article mentions that TSMC seems to have the best numbers, though at higher per-die cost than the authors expected or found reasonable.

Right, that's the spin. You have to put a "seems to" on "have the best numbers" because there are no numbers . If there numbers were the "best", then they would give them. They did not. So... they probably aren't. Or there are other complexities they don't want to reveal.

No, that’s not how it works.

TSMC publishes industrial research, not pure science research like a university.

In this context the amount of detail they release is careful balance of PR benefit vs. competitive advantage vs. patent status vs. keeping their talent happy because good researches want their names in prestigious journals.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#63

Post by adrian_b »

ksec wrote: post #59
Red_Comet_88 wrote: post #54

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…

N3B is used by Intel for its Lunar Lake, Arrow Lake S and Arrow Lake H CPUs and GPUs, so it is also in full production for high-power non-small and non-mobile chips.

Of course, even if N3B is fine for desktop CPUs and for smaller GPUs, it may still have too low yields for chips of the size of the top models of NVIDIA GPUs.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#64

Post by nsteel »

ksec wrote: post #59
Red_Comet_88 wrote: post #54

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…

This. The IP they need, specifically the SerDes, isn't available for 3nm (n3e) yet. That stuff isn't required for consumer devices, it comes later.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#65

Post by nsteel »

adrian_b wrote: post #63
ksec wrote: post #59

Earlier quoted context omitted.

N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…

N3B is used by Intel for its Lunar Lake, Arrow Lake S and Arrow Lake H CPUs and GPUs, so it is also in full production for high-power non-small and non-mobile chips. Of course, even if N3B is fine for desktop CPUs and for smaller GPUs, it may still have too low yields for chips of the size of the top models of NVIDIA GPUs.

Anything serious is using n3e.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#66

Post by ajross »

WhitneyLand wrote: post #62
ajross wrote: post #29

Earlier quoted context omitted.

Right, that's the spin. You have to put a "seems to" on "have the best numbers" because there are no numbers . If there numbers were the "best", then they would give them. They did not. So... they probably aren't. Or there are other complexities they don't want to reveal.

No, that’s not how it works. TSMC publishes industrial research, not pure science research like a university. In this context the amount of detail they release is careful balance of PR benefit vs. competitive advantage vs. patent status vs. keeping their talent happy because good researches want their names in prestigious journals.

Please. "What is the fin pitch of the process you're releasing next quarter?" is hardly an IP-compromising secret. This stuff is and always has been routine disclosure in advance of technology revisions, analogous to "Our Next Software Version Will Support X and Y". You can excuse it if you insist, but it's pretty clear that we're being primed for 2nm to be at most an incremental improvement.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#67

Post by JackYoustra »

nsteel wrote: post #64
ksec wrote: post #59

Earlier quoted context omitted.

N3 is mature and is already in full production for small Mobile SoC only. The Blackwell goes up to ~750mm2 it is a completely different beast. And Nvidia is already having trouble trying to fill up their Blackwell on a higher capacity, relatively mature N4 Node. Imagine doing it on an expensive N3, and then charge $4999 only to get outrage as rip off on HN and reddit. Generally speaking the larger die size, high perf…

This. The IP they need, specifically the SerDes, isn't available for 3nm (n3e) yet. That stuff isn't required for consumer devices, it comes later.

I'm not familiar with the process enough to even know what to search here, do you have some recommended reading materials about how IP becomes available for different processes and what the engineering difficulties / process is, especially for different types of IP?

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#68

Post by nsteel »

ajross wrote: post #66
WhitneyLand wrote: post #62

Earlier quoted context omitted.

No, that’s not how it works. TSMC publishes industrial research, not pure science research like a university. In this context the amount of detail they release is careful balance of PR benefit vs. competitive advantage vs. patent status vs. keeping their talent happy because good researches want their names in prestigious journals.

Please. "What is the fin pitch of the process you're releasing next quarter?" is hardly an IP-compromising secret. This stuff is and always has been routine disclosure in advance of technology revisions, analogous to "Our Next Software Version Will Support X and Y". You can excuse it if you insist, but it's pretty clear that we're being primed for 2nm to be at most an incremental improvement.

Does the undisputed market leader need to advertise like this? There's no other gig in town. Samsung can't yield, Intel is... Yeh.

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#69

Post by notnullorvoid »

Red_Comet_88 wrote: post #54

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

US push for local manufacturing might play into that a bit since TSMC's Arizona fab only just started producing 4nm. Nvidia is planning to provide GPUs for major US datacenter expansion, so using locally produced chips should help significantly (especially if the chip tariffs end up becoming a reality).

Re: TSMC 2nm Process Disclosure – How Does It Measure Up?

#70

Post by tiffanyh »

Red_Comet_88 wrote: post #54

Does anyone know why Nvidia chose to re-use the 4N process for their Blackwell series? From everything I've read, 3N is mature and is already in full production, yet Nvidia chose to just reuse 4N. It seems very much unlike Nvidia to leave performance on the table.

Doesn't Apple pay for exclusive access to N, and N+1 nodes ... shutting everyone else out from using newer node sizes.
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