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100x defect tolerance: How we solved the yield problem

cerebras.ai

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Re: 100x defect tolerance: How we solved the yield problem

#41

Post by ajb »

axus wrote: post #25
sroussey wrote: post #15

Earlier quoted context omitted.

I wonder if you could… just not cut the wafer at all??

Might be jumping in without reading, but the chips you cut out of the wafer have to be delivered to physically different locations.

Normally yes. But they're using a whole wafer for a single chip! So it's actually a good idea.

I guess the issue is how do you design your routing fabric to work in the edge regions.

Actually I wonder how they are exposing this wafer. Normal chips are exposed in a rectangular batch called a reticle. The reticle mask has repeated patterns across it, and it is then exposed repeatedly across the wafer. So either they have to make a reticle mask the full size of the wafer, which sounds expensive, or they somehow have to precisely align reticle exposures so that the joined edges form valid circuits.

Re: 100x defect tolerance: How we solved the yield problem

#42

Post by kristjansson »

ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Additional wafer area would be a marginal increase in performance (+~20% core core best case) but increases the complexity of their design, and requires they figure out how to package/connect/house/etc. a non-standard shape. A wafer scale chip is already a huge tech risk, why spend more novelty budget on nonessential weirdness?

Re: 100x defect tolerance: How we solved the yield problem

#43

Post by bigmattystyles »

dylan604 wrote: post #37
bigmattystyles wrote: post #30

When I was a kid, I used to get intel keychains with a die in acrylic - good job to whoever thought of that to sell the fully defective chips.

wow, fancy with the acrylic. lots of places just place a chip (I'm more familiar with RAM sticks) on a keychain and call it a day.

they're all over eBay, I just checked - the one I was thinking of, that I think I had is going for $150 - the things you get rid of....

Re: 100x defect tolerance: How we solved the yield problem

#45

Post by ungreased0675 »

ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

Why does it have to be a square? There’s no need to worry about interchangeable third-party heat sink compatibility. Is it possible to make it an irregular polygon instead of square?

Re: 100x defect tolerance: How we solved the yield problem

#46

Post by yannyu »

mattashii wrote: post #24
yannyu wrote: post #9

Earlier quoted context omitted.

> I assume they don't pattern the unused area, so the process should be quicker? The primary driver of time and cost in the fabrication process is the number of layers for the wafers, not the surface area, since all wafers going through a given process are the same size. So you generally want to maximize the number of devices per wafer, because a large part of your costs will be calculated at the per-wafer level, not…

Yes, but isn't a big driver of layer costs the cost of the machines to build those layers? For patterning, a single iteration could be (example values, no actual values used, probably only ballpark accuracy) on a 300M$ EUV machine with 5-year write off cycle, patterns on average 180 full wafers /hour. Excluding energy usage and service time, each wafer that needs full patterning would cost ~38$. If each wafer only ne…

> Yes, but isn't a big driver of layer costs the cost of the machines to build those layers?

Let's say the time spent in lithography step is linear the way you're describing. Even with that, the deposition step beforehand is surface area independent and would be applied across the entire wafer, and takes just as long if not longer than the lithography.

Additionally, if you were going to build a fab ground up for some specific purpose, then you might optimize the fab for those specific devices as you lay out. But most of these companies are not doing that and are simply going through TSMC or a similar subcontractor. So you've got an additional question of how far TSMC will go to accommodate customers who only want to use half a wafer, and whether that's the kind of project they could profitably cater to.

Re: 100x defect tolerance: How we solved the yield problem

#47

Post by kristjansson »

sroussey wrote: post #14
ajb wrote: post #4

So they massively reduce the area lost to defects per wafer, from 361 to 2.2 square mm. But from the figures in this blog, this is massively outweighed by the fact that they only get 46222 sq mm useable area out of the wafer, as opposed to 56247 that the H100 gets - because they are using a single square die instead of filling the circular wafer with smaller square dies, they lose 10,025 sq mm! Not sure how that's a…

It’s a win if you can use the wafer as opposed to throwing it away.

A win is a manufacturing process that results in a functioning product. Wafers, etc. aren't so scarce as to demand every mm2 be used on every one every time.

Re: 100x defect tolerance: How we solved the yield problem

#48

Post by anonymousDan »

Very interesting. Am I correct in saying that fault tolerance here is with respect to 'static' errors that occur during manufacturing and are straightforward to detect before reaching the customer? Or can these failures potentially occur later on (and be tolerated) during the normal life of the chip?

Re: 100x defect tolerance: How we solved the yield problem

#49

Post by bradyd »

bigmattystyles wrote: post #43
dylan604 wrote: post #37

Earlier quoted context omitted.

wow, fancy with the acrylic. lots of places just place a chip (I'm more familiar with RAM sticks) on a keychain and call it a day.

they're all over eBay, I just checked - the one I was thinking of, that I think I had is going for $150 - the things you get rid of....

Electronic Goldmine sells entire scrapped 200mm wafers for $15 or less

https://theelectronicgoldmine.com/search?options%5Bprefix%5D...

Re: 100x defect tolerance: How we solved the yield problem

#50

Post by bentcorner »

lostlogin wrote: post #31
NickHoff wrote: post #27

Neat. What about power density? An H100 has a TDP of 700 watts (for the SXM5 version). With a die size of 814 mm^2 that's 0.86 W/mm^2. If the cerebras chip has the same power density, that means a cerebras TDP of 37.8 kW. That's a lot. Let's say you cover the whole die area of the chip with water 1 cm deep. How long would it take to boil the water starting from room temperature (20 degrees C)? amount of water = (die…

If rack mounted, you are ending up with something like a reverse power station. So why not use it as an energy source? Spin a turbine.

I'm aware of the efficiency losses but I think it would be amusing to use that turbine to help power the machine generating the heat.
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