Gate-level simulation of ASIC in browser

Post by Taniwha » Fri, Jan 10, 2025, 12:51 AM UTC

Lerc wrote: post #29

Taniwha wrote: post #27

Earlier quoted context omitted.

(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc) I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons. Yes you can get better performance and density by laying polygons, especially stuff like ROMs…

How about if I'm a masochist :) I do have form when it comes to the needlessly complicatedly making things small like impenetrable programs that fit in a url https://c50.fingswotidun.com/show/?code=z1s-xy*dee%2B%2B2*z!... Polygon level seems more akin to machine code than asm. That is (usually) a step too far for me. Very tempted to do something for tiny_tapeout, it does seem the kind of nerd sniping aimed at me. I'm…

Mostly I'm just trying to explain just how (relatively) hard things are, so people wont get too far out of their depth. I'd really recommend doing the usual HLL/assembler approach - start with a verilog only implementation, build a test bench (tiny tapeout has infrastructure for this), look at the bits you want to be faster/denser, try a hand compiled gates implementation (you can do this within verilog for a start), then maybe even hand lay it out

Yes, I live south of you in Dunedin, though I worked in the SF Bay Area for a couple of decades doing all sorts of stuff including chips, OS's, embedded crypto stuff etc

Post by therealcamino » Fri, Jan 10, 2025, 1:22 AM UTC

Lerc wrote: post #29

Taniwha wrote: post #27

Earlier quoted context omitted.

(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc) I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons. Yes you can get better performance and density by laying polygons, especially stuff like ROMs…

How about if I'm a masochist :) I do have form when it comes to the needlessly complicatedly making things small like impenetrable programs that fit in a url https://c50.fingswotidun.com/show/?code=z1s-xy*dee%2B%2B2*z!... Polygon level seems more akin to machine code than asm. That is (usually) a step too far for me. Very tempted to do something for tiny_tapeout, it does seem the kind of nerd sniping aimed at me. I'm…

If you want to do low level design, you can look at the Micro Magic public domain tool set. As someone said above, Verilog only describes the logical function (ranging from the RTL level to the gate level.) You'd need other tools to work on everything physical, like placement and routing.

https://github.com/yarpose/YARPOSE.Micromagic_PD

Re: Gate-level simulation of ASIC in browser

Re: Gate-level simulation of ASIC in browser