Completely wild to me that you are backing out the netlist from the geometry gds.
Gate-level simulation of ASIC in browser
21–30 of 32 posts
Re: Gate-level simulation of ASIC in browser
#22Completely wild to me that you are backing out the netlist from the geometry gds.
First I implemented it, and then learned that it is called Layout vs Schematic (LVS). For now automatic conversion is limited to stateless cells, but I'm planning to rewrite the circuit extractor to support all flipflops and latches.
Re: Gate-level simulation of ASIC in browser
#23Earlier quoted context omitted.
Verilog describes the logic. This is extremely simplified, but you can imagine that verilog and other HDLs are "compiled" into a big schematic of logic gates and a big list of signal timing constraints between them. From that schematic and constraint list, a solver then works to do place and route. Both of these intermediate stages between verilog and the final working hardware are where all of the secret sauce in se…
That's all very analogous to software compilers, but doesn't really answer the question I had. Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there. Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get…
Can be huge depending how low level you are allowed to go. For example from recent
38C3 - The Design Decisions behind the first Open-Everything FABulous FPGA https://www.youtube.com/watch?v=3Lll9_-gYGg
there was a mention of using open source SRAM library versus Siemens one. Open source macros build 1KB 12MHz ram while siemens is 3x capacity 100MHz
https://youtu.be/3Lll9_-gYGg?feature=shared&t=1740
Siemens delivers this by breaking foundry design rules :)
Re: Gate-level simulation of ASIC in browser
#24Earlier quoted context omitted.
You can do it too, come on over to https://www.tinytapeout.com/
Interesting: https://www.tinytapeout.com/competitions/demoscene-tt10/ This seems to be the currently open tapeout. How low-level can you go with tinytapeout? One can imagine the insanity of doing a manual layout to push a demo to extremes.
Those baseball caps are BALLIN
Re: Gate-level simulation of ASIC in browser
#25How many gates are here?
Is it near the crossover of where the same amount of logic can implement a tiny CPU which can run a program to generate the same output?
(I guess not in this case, because it needs to output 18 million pixels per second, and a micro-CPU probably won't be doing that anytime soon)
Re: Gate-level simulation of ASIC in browser
#26Re: Gate-level simulation of ASIC in browser
#27Earlier quoted context omitted.
Verilog describes the logic. This is extremely simplified, but you can imagine that verilog and other HDLs are "compiled" into a big schematic of logic gates and a big list of signal timing constraints between them. From that schematic and constraint list, a solver then works to do place and route. Both of these intermediate stages between verilog and the final working hardware are where all of the secret sauce in se…
That's all very analogous to software compilers, but doesn't really answer the question I had. Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there. Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get…
(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc)
I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons.
Yes you can get better performance and density by laying polygons, especially stuff like ROMs and RAMs and regular ALU structures, but it's a lot of work and not a rathole you want to go down as a beginner
Re: Gate-level simulation of ASIC in browser
#28Earlier quoted context omitted.
This is going to sound quaint, but because of this simulation, this is the first time I realized they're _literal_ flags on the sides of the CPU, which is blowing my mind.
You mean the pads? Those are the connection points for the wires that connect to the external package pins.
Unless they are hooked directly to little Swiss clock figurines holding semaphores. At that point you’d kinda have the amazing human CPU from Three Body Problem.
Re: Gate-level simulation of ASIC in browser
#29Earlier quoted context omitted.
That's all very analogous to software compilers, but doesn't really answer the question I had. Specifically for Tiny Tapeout, how much is there to be gained by going low level? I feel like using a subset of verilog features might get you most of the way there. Consider that there is a 512 byte BASIC interpreter in asm, that's well beyond what a compiler could manage. I would expect logic expressions in verilog to get…
(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc) I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons. Yes you can get better performance and density by laying polygons, especially stuff like ROMs…
How about if I'm a masochist :)
I do have form when it comes to the needlessly complicatedly making things small like impenetrable programs that fit in a url https://c50.fingswotidun.com/show/?code=z1s-xy*dee%2B%2B2*z!...
Polygon level seems more akin to machine code than asm. That is (usually) a step too far for me.
Very tempted to do something for tiny_tapeout, it does seem the kind of nerd sniping aimed at me.
I'm going to take a stab and say judging from your username, you are vaguely near me (Chch).
Re: Gate-level simulation of ASIC in browser
#30Earlier quoted context omitted.
(I've written Verilog compilers, normal compilers, designed gates and chips, can read polygons, written assembler, etc etc) I think it is all very analogous to software compilers, but IMHO writing in assembler is an order of magnitude easier than manually laying gates, and maybe 2-3 orders more than manually laying polygons. Yes you can get better performance and density by laying polygons, especially stuff like ROMs…
How about if I'm a masochist :) I do have form when it comes to the needlessly complicatedly making things small like impenetrable programs that fit in a url https://c50.fingswotidun.com/show/?code=z1s-xy*dee%2B%2B2*z!... Polygon level seems more akin to machine code than asm. That is (usually) a step too far for me. Very tempted to do something for tiny_tapeout, it does seem the kind of nerd sniping aimed at me. I'm…
If we're talking nerd sniping: A polygon layout for an analog computer that directly generates the RGB analog VGA signals. :-)
(Must resist...)