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In preparation for this, I've been reading up on ARM's looser memory consistency model, and C++'s rules regarding this. It's been pretty eye-opening.
I'm looking forward to seeing how much that ARM codebase takes advantage of the weaker guarantees that ARM permits. It seems like a trade-off of scalability vs. correct-code complexity.
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Probably "A Primer on Memory Consistency and Cache Coherence"
Hi, would you recommend this book in 2024?
The programming-language-specific parts are more focused on C than C++ (which is my main focus), but I've still found it quite helpful.
I haven't looked at the other sources people are mentioning though, so no idea how it compares.
[0] https://cdn.kernel.org/pub/linux/kernel/people/paulmck/perfb...
Earlier quoted context omitted.
Hi, would you recommend this book in 2024?
FWIW, most of my recent knowledge on this topic comes from [0]. The programming-language-specific parts are more focused on C than C++ (which is my main focus), but I've still found it quite helpful. I haven't looked at the other sources people are mentioning though, so no idea how it compares. [0] https://cdn.kernel.org/pub/linux/kernel/people/paulmck/perfb...
Earlier quoted context omitted.
FWIW, most of my recent knowledge on this topic comes from [0]. The programming-language-specific parts are more focused on C than C++ (which is my main focus), but I've still found it quite helpful. I haven't looked at the other sources people are mentioning though, so no idea how it compares. [0] https://cdn.kernel.org/pub/linux/kernel/people/paulmck/perfb...
Thank you, I will give your resource a read :)
At least for me, it requires (a) a good reason for powering through it, (b) a good night's sleep, and (c) Adderall :)
Just saying, it may not be the most effective / efficient way to learn what you want to know.
Earlier quoted context omitted.
Thank you, I will give your resource a read :)
You're welcome! But it's not a quick read. At least for me, it requires (a) a good reason for powering through it, (b) a good night's sleep, and (c) Adderall :) Just saying, it may not be the most effective / efficient way to learn what you want to know.
I was taught that a deeper understanding leads to better software/solutions and I strive to live up to my mentor dedication :)
Earlier quoted context omitted.
You're welcome! But it's not a quick read. At least for me, it requires (a) a good reason for powering through it, (b) a good night's sleep, and (c) Adderall :) Just saying, it may not be the most effective / efficient way to learn what you want to know.
Ahaha, luckily /s I am a bit of a weirdo and I like to delve deeper into things related to my job. I was taught that a deeper understanding leads to better software/solutions and I strive to live up to my mentor dedication :)
aside from being fun, it just makes everything so much easier when it's not "magic"
> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution. > Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they…
Just to clarify your comment via a question: are you pointing out that barrier instructions are a scheduling ‘issue’ that the processor uses to order instructions versus something like a memory read that actually requires a pause in the execution of instructions?