Memory Consistency Models: A Tutorial
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Memory Consistency Models: A Tutorial
1–10 of 19 posts
Re: Memory Consistency Models: A Tutorial
#2what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ?
it seems to be coming up kinda 404 for me. thank you !
Re: Memory Consistency Models: A Tutorial
#3what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ? it seems to be coming up kinda 404 for me. thank you !
Probably "A Primer on Memory Consistency
and Cache Coherence"
Re: Memory Consistency Models: A Tutorial
#4what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ? it seems to be coming up kinda 404 for me. thank you !
See also https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/p... and Gharachorloo's thesis paper.
Re: Memory Consistency Models: A Tutorial
#5> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution.
> Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they can cost hundreds of cycles.
I may be wrong, but I think to readers who do not already know what barriers do and are, this makes barriers seem like blocking behaviours.
Re: Memory Consistency Models: A Tutorial
#6what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ? it seems to be coming up kinda 404 for me. thank you !
See also https://www.cs.cmu.edu/afs/cs/academic/class/15740-f18/www/p... and Gharachorloo's thesis paper.
@sdbbp, thank you kindly for the references, both are excellent !
Re: Memory Consistency Models: A Tutorial
#7> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution. > Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they…
Just to clarify your comment via a question: are you pointing out that barrier instructions are a scheduling ‘issue’ that the processor uses to order instructions versus something like a memory read that actually requires a pause in the execution of instructions?
Re: Memory Consistency Models: A Tutorial
#8what is the "dense tome" that the author refers to in this link: http://www.morganclaypool.com/doi/abs/10.2200/S00346ED1V01Y2... ? it seems to be coming up kinda 404 for me. thank you !
Probably "A Primer on Memory Consistency and Cache Coherence"
Hi, would you recommend this book in 2024?
Re: Memory Consistency Models: A Tutorial
#9> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution. > Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they…
Barriers can induce blocking behavior though. A store barrier followed by a store operation can result in a blocking operation until the store buffer is flushed, and similarly for a load barrier.
Re: Memory Consistency Models: A Tutorial
#10> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution. > Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they…
The usual way that barriers were implemented was to simply stall the CPU pipeline. So yes, they do indeed have blocking semantics. IIRC mfence still does stall the pipeline on x86, but I think the CPU is a bit smarter for locked instructions.