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Zilog Z80 CPU – Modern, free and open source silicon clone

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Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#61

Post by Someone »

unnah wrote: post #35
Someone wrote: post #30

Earlier quoted context omitted.

https://en.wikipedia.org/wiki/Pentium_III#Katmai : “The Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache (which adds 25 million transistors), and has dimensions of 12.3 mm by 10.4 mm (128 mm²). It is fabricated in Intel's P856.5 process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with five levels of aluminum interconnect” That’s 2,000 times the area of this 0.064 mm²…

On that kind of process, you could make a 1024-core Z80 machine, leaving half the area for memory, interconnect and I/O. With suitably smart programming and an embarrassingly parallel problem, it might even be able to beat a Pentium III in performance... although it looks like the single-core Pentium III can run 128-bit SSE instructions at 2 cycles per instruction.

Suitably smart programming and a problem that suits the hardware. I doubt there are many of the latter.

A Z80 has a 4-bit ALU (https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture), making even integer addition take quite a few cycles (15 for 16-bit addition, reading http://www.z80.info/z80time.txt)

And then there’s the clock speed difference. The first Pentium III ran at 450MHz, the fastest Z80 at 50MHz (https://en.wikipedia.org/wiki/Zilog_eZ80)

I think those two combined already will cost you a factor of around 100 in speed versus that pipelined Z80, much more versus a Z80 proper.

Things get worse if you want to add or subtract 32- or 64-bit integers (another factor of 2 or 4, ballpark)

If you want to do integer multiplication and division of any size and all floating point operations you will have to do those in software, and likely lose whatever speed advantage you might still have.

O, and each core will be limited to 64kB of memory. Those interconnects better be fast and use DMA, so you can keep computing while you shuffle data around.

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#62

Post by karelpeeters »

flohofwoe wrote: post #48
rowanG077 wrote: post #44

Earlier quoted context omitted.

Just because this is done in verilog doesn't make it emulation. It's probably just machine placed and routed. Almost everything is these days in digital design.

But look here, it's even doing a switch-case over the opcode, which is very typical for a software CPU emulator: https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... Instruction decoding on a real Z80 CPU doesn't work at all like that :) A non-emulator-approach would probably use the reverse engineered Z80 netlist from visual6502.org to base the design on, no idea if this is even doable with modern chip de…

That switch-case gets optimized and compiled down to logic gates by the synthesis tools. It'll be a different set of gates from the original netlist (which might also have used a more regular grid structure for this), but it won't be _that_ different. It's not somehow running this switch-case in software emulation on a different CPU instantiated in this design.

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#63

Post by codebje »

flohofwoe wrote: post #48
rowanG077 wrote: post #44

Earlier quoted context omitted.

Just because this is done in verilog doesn't make it emulation. It's probably just machine placed and routed. Almost everything is these days in digital design.

But look here, it's even doing a switch-case over the opcode, which is very typical for a software CPU emulator: https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... Instruction decoding on a real Z80 CPU doesn't work at all like that :) A non-emulator-approach would probably use the reverse engineered Z80 netlist from visual6502.org to base the design on, no idea if this is even doable with modern chip de…

Instruction decoding on a real Z80 CPU works pretty much like that, as it happens. There's a big PLA table that takes the IR inputs and a handful of other control signals (like "is 0xED prefixed") and lights up output control signals to say what the instruction to be executed is. See https://static.righto.com/files/z80-pla-table.html for this table laid out nicely.

Verilog isn't imperative code, to be executed one line after another in sequence. It's a description of combinatorial logic to be wired up to inputs and outputs, gated by a clock edge. Everything in the Verilog module "runs" at the same time, there's no jumping to a branch, there is instead logic to wire up one "casez" block or another to the relevant output signals. All the blocks are lit up, only one has its output selected to connect to the output wires.

The PLA block is more convenient to a hardware engineer laying out a CPU by hand. You can see everything together and trace execution easily. Downstream consequences of decode are done elsewhere. Upstream decode of control signals are done elsewhere. The Verilog is more convenient to a hardware engineer relying on tools to route logic: the Verilog does more than the PLA - it does the additional control signal inputs, and it does the downstream consequences like determining which register(s) are used on which register bus. It's laid out more like a software decode of the instruction bits because it's easier to think about groups of opcodes than individual ones.

In execution, though, they wind up doing very similar things.

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#64

Post by Andrex »

belter wrote: post #3

Z80 was the CPU of the ZX Spectrum. Oh the memories... https://en.wikipedia.org/wiki/ZX_Spectrum

I thought it was used for the Game Boy, but apparently while there are many similarities they're basically incompatible[0].

0. https://forums.nesdev.org/viewtopic.php?t=18335

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#65

Post by LeFantome »

belter wrote: post #3

Z80 was the CPU of the ZX Spectrum. Oh the memories... https://en.wikipedia.org/wiki/ZX_Spectrum

It was also the CPU in my first computer--the Coleco ADAM: https://en.wikipedia.org/wiki/Coleco_Adam

I still have my copy of Programming the Z80 that I got as a kid: https://en.wikipedia.org/wiki/Programming_the_Z80

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#66

Post by Someone »

Retr0id wrote: post #58
Dwedit wrote: post #41

Earlier quoted context omitted.

If you were designing a new compatible processor for older systems, the limiting factor would be the memory bus. A cache would be necessary to get high speeds. The cache would need to know about all bank-switching performed by the system, and understand how the memory banks are mapped into the memory space. Could have: * Plain read-only memory (you cache this) * Plain RAM not shared with other devices (you cache this…

IIRC this is what the people making swap-in accelerators for 6502 chess computers are doing

Because it’s easy to ‘cache’ the entire memory of the host system, it’s better described as a new computer that only slows down to access the memory locations that affect I/O (video, audio, keyboard, I/O ports, etc.)

https://www.e-basteln.de/computing/65f02/65f02/:

“The idea is to use this as a “universal” accelerator for 6502 and 65C02-based host computers – just plug it into the CPU socket. The only thing the FPGA board needs to know about its host is the memory map: Where does the host have memory-mapped I/O? Up to 16 different memory maps can be stored in the FPGA, and selected via a mini DIP switch. Upon power-on, the 65F02 grabs the complete RAM and ROM content from the host and copies it into the on-chip RAM, except for the I/O area. Then the CPU gets going, using the internal memory at 100 MHz for all bus accesses except for any I/O addresses – for these, the internal CPU pauses, and an external bus cycle is started at whatever the external clock speed is.”

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#67

Post by unnah »

Someone wrote: post #61
unnah wrote: post #35

Earlier quoted context omitted.

On that kind of process, you could make a 1024-core Z80 machine, leaving half the area for memory, interconnect and I/O. With suitably smart programming and an embarrassingly parallel problem, it might even be able to beat a Pentium III in performance... although it looks like the single-core Pentium III can run 128-bit SSE instructions at 2 cycles per instruction.

Suitably smart programming and a problem that suits the hardware. I doubt there are many of the latter. A Z80 has a 4-bit ALU ( https://en.wikipedia.org/wiki/Zilog_Z80#Microarchitecture ), making even integer addition take quite a few cycles (15 for 16-bit addition, reading http://www.z80.info/z80time.txt ) And then there’s the clock speed difference. The first Pentium III ran at 450MHz, the fastest Z80 at 50MHz ( ht…

Yes, there are definitely challenges, and there must be a reason no one is seriously selling 1024-core versions of old 8-bit processors... but perhaps on an Intel 130 nm process you could make a faster Z80 than just 50 MHz. Quick googling didn't reveal what process Zilog is currently using for eZ80.

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#68

Post by Vogtinator »

flohofwoe wrote: post #29
Koshkin wrote: post #11

I couldn’t help but notice that the circuit layout looks like a uniform gate array rather something resembling a custom layout you usually see in die photos.

Because it's a Verilog implementation which is much closer to a software CPU emulator than the real thing (e.g. it has nothing to do with the original Z80 "transistor layout"). For instance here's the LD A,(DE) "instruction payload": https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... And here's the same machine cycle in my software emulator: https://github.com/floooh/chips/blob/bd1ecff58337574bb46eba5...…

It only looks like that if you treat it as a C-like programming language, which it is not. Unless specified otherwise, all the statements are "executed" in parallel by the synthesized logic. There is no emulation.

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#69

Post by flohofwoe »

codebje wrote: post #63
flohofwoe wrote: post #48

Earlier quoted context omitted.

But look here, it's even doing a switch-case over the opcode, which is very typical for a software CPU emulator: https://github.com/rejunity/z80-open-silicon/blob/974c7711b2... Instruction decoding on a real Z80 CPU doesn't work at all like that :) A non-emulator-approach would probably use the reverse engineered Z80 netlist from visual6502.org to base the design on, no idea if this is even doable with modern chip de…

Instruction decoding on a real Z80 CPU works pretty much like that, as it happens. There's a big PLA table that takes the IR inputs and a handful of other control signals (like "is 0xED prefixed") and lights up output control signals to say what the instruction to be executed is. See https://static.righto.com/files/z80-pla-table.html for this table laid out nicely. Verilog isn't imperative code, to be executed one li…

Thanks a lot for the thorough explanation, much appreciated!

Re: Zilog Z80 CPU – Modern, free and open source silicon clone

#70

Post by londons_explore »

ein0p wrote: post #38
phendrenad2 wrote: post #32

I wonder if this will ever be priced competitively with the massive number of used or NOS Z80 chips out in the wild.

eBay says a Chinese Z80 clone is less than $4 with free shipping. This isn’t even going to be competitive with lower end FPGAs. It’s more of a fun “why not” type of project.

How do those clones work? Are they asics, or microcontrollers/fpga's which do emulation?
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