Live data from Hacker News

TSMC unveils 1.6nm process technology with backside power delivery

tomshardware.com

181–190 of 209 posts

Re: TSMC unveils 1.6nm process technology with backside power delivery

#181
post #125

Earlier quoted context omitted.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimization…

How is this kind of software developed without becoming a massive pile of spaghetti code?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#182
post #125

Earlier quoted context omitted.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimization…

Heh, as long as you're not talking about UX...

Re: TSMC unveils 1.6nm process technology with backside power delivery

#183
post #34
post #16

Earlier quoted context omitted.

the pics go to 404

thanks, I've fixed them btw, you appear to be shadow banned, probably on account of being downvoted for making short comments like "good" or "I don't get it" Short & simple responses may be adequate at times, but usually people will view it as not adding anything Perhaps reviewing guidelines https://news.ycombinator.com/newsguidelines.html will give an idea of the ideal being yearned for (granted, it's an ideal). In…

fuck censorship

Re: TSMC unveils 1.6nm process technology with backside power delivery

#184
post #162

Earlier quoted context omitted.

Reminiscent of the Java CPUs: Not even used for embedded (ironically the reason Java was created?). And not used at all by the massive Java compute needed for corporate software worldwide?

Weren't they used in Java Cards? Basically, every single credit card sized security chip (including actual credit cards, of course) is a small processor running Java applets. Pretty much everyone has one or more in their wallet. I'd assume those were actual Java CPUs directly executing bytecode?

No, credit cards do not have CPUs or run Java code.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#185
post #162

Earlier quoted context omitted.

Weren't they used in Java Cards? Basically, every single credit card sized security chip (including actual credit cards, of course) is a small processor running Java applets. Pretty much everyone has one or more in their wallet. I'd assume those were actual Java CPUs directly executing bytecode?

> Weren't they used in Java Cards? Not sure: https://en.wikipedia.org/wiki/Java_processor doesn't seem to mention any in current use. I am ignorant of the actual correct answer: I had simply presumed it is simpler to write the virtual machine using a commercial ISA than to develop a custom ISA. Java Card bytecode run by the Java Card Virtual Machine is a functional subset of Java 2 bytecode run by a standard Java Vir…

picoJava processors (Sun Microsystems) https://www.cnet.com/culture/sun-releases-complete-chip-desi...

Patriot Scientific's Ignite processor family https://www.cpushack.com/2013/03/02/chuck-moore-part-2-from-...

ARM Jazelle technology https://developer.arm.com/documentation/ddi0222/b/introducti...

https://www.eetimes.com/nazomi-offers-plug-in-java-accelerat...

It's all dot-com era stuff and Sun Microsystems also created a Java OS that could run directly on hardware without a host operating system.

That's about it

Re: TSMC unveils 1.6nm process technology with backside power delivery

#186

Earlier quoted context omitted.

"Likely better" doesn't come from 14A vs 16A. It comes from Intel using High NA-EUV vs TSMC using double pattern Low NA-EUV. If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

I am not sure where that would come from. There is nothing about dsa that means this. Dsa is one of many patterning assist technologies, just...an old one. Neat, but not 'new'. You use patterning assist to make smaller, more regular features, which is exactly what the 16a vs 18a refers to. That has somewhat less to do with performance, which is tied as much to material, stress, and interface parameters. Nothing gets…

DSA is what is going to make it possible for Intel to compete at all. Without it, they are going to have fancy machines in fancy foundries that are too expensive to attract any customers.

To the best of my knowledge, DSA never made it out of the lab.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#187
post #98

Earlier quoted context omitted.

Wait till you talk to theoretical physicists who set c=h-bar=1.

I have more fundamental concerns to talk with a theoretical physicist about first :D Time to kick an ants nest here... Quantum mechanics is a useless study that had no business being a scientific field. The most fundamental principles, like quantum superposition, can never be tested or validated and therefore could never be used to be predictive of anything other than similarly theoretical ideas.

Shut up and calculate.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#188
post #98

Earlier quoted context omitted.

Wait till you talk to theoretical physicists who set c=h-bar=1.

I don’t think they drop the dimensions, just the constants.

It's equivalent to the 1.6nm != 1.6 nm though.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#189
post #46

Earlier quoted context omitted.

You're the one calling it a feature size, not TSMC.

They're the ones specifying units.

I'm begging even 1 person in this thread to do even 5 minutes of research on where these numbers come from.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#190
post #145

Earlier quoted context omitted.

200 million transistors per square millimeter. Gallons per mile only makes sense when you are talking about dragsters.

gallons per hundred miles make much more sense than that. incidentally, this is the measure rest of the world is advertising, except usually in liters per 100km. there's a good reason for this: comparisons linear instead of inversely proportional. 6l/100km is 50% better than 9l/100km. 30mpg vs 20mpg is... not as simple.

>30mpg vs 20mpg is... not as simple.

How so?

Post reply on HN