Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

TSMC unveils 1.6nm process technology with backside power delivery

tomshardware.com

Post reply on HN
Print view View original

161–170 of 209 posts

Re: TSMC unveils 1.6nm process technology with backside power delivery

#161

Post by _heimdall »

exe34 wrote: post #98
_heimdall wrote: post #48

Earlier quoted context omitted.

They're using the wrong units if we need to consider the nanometer as something other than a measure of distance.

Wait till you talk to theoretical physicists who set c=h-bar=1.

I have more fundamental concerns to talk with a theoretical physicist about first :D

Time to kick an ants nest here...

Quantum mechanics is a useless study that had no business being a scientific field. The most fundamental principles, like quantum superposition, can never be tested or validated and therefore could never be used to be predictive of anything other than similarly theoretical ideas.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#162

Post by crote »

robocat wrote: post #151
merb wrote: post #132

Earlier quoted context omitted.

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

Reminiscent of the Java CPUs: Not even used for embedded (ironically the reason Java was created?). And not used at all by the massive Java compute needed for corporate software worldwide?

Weren't they used in Java Cards?

Basically, every single credit card sized security chip (including actual credit cards, of course) is a small processor running Java applets. Pretty much everyone has one or more in their wallet. I'd assume those were actual Java CPUs directly executing bytecode?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#163

Post by tivert »

Workaccount2 wrote: post #150
Sysreq2 wrote: post #95

Earlier quoted context omitted.

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

"Likely better" doesn't come from 14A vs 16A. It comes from Intel using High NA-EUV vs TSMC using double pattern Low NA-EUV. If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

> If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

Is Intel working on "an optimized older generation" as a backup plan? I don't follow semiconductors very closely, but my impression is the reason they're "behind" is they bet aggressively on an advanced technology that didn't pan out.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#164

Post by Golden_Wind123 »

tivert wrote: post #163
Workaccount2 wrote: post #150

Earlier quoted context omitted.

"Likely better" doesn't come from 14A vs 16A. It comes from Intel using High NA-EUV vs TSMC using double pattern Low NA-EUV. If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better.

> If Intel pulls off DSA, they will be using a newer generation of technology compared to TSMC using an optimized older generation. Could TSMC still make better chips? Maybe. But Intel will likely be better. Is Intel working on "an optimized older generation" as a backup plan? I don't follow semiconductors very closely, but my impression is the reason they're "behind" is they bet aggressively on an advanced technolog…

From what I remember the aprocyphal story is that Intel dragged their feet on adopting EUV and instead tried to push multi-patterning past it's reasonable limits.

If that's the actual root cause, then Intel's lagging is due to optimizing their balance sheets (investors like low capital expenditures) at the expense of their technology dominance.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#165

Post by martinpw »

Sysreq2 wrote: post #95
Workaccount2 wrote: post #63

Earlier quoted context omitted.

Intel has a 1.4nm process in the pipeline for ~2027. They just took delivery on their first high NA EUV machine in order to start working on it. Their gamble however is that they need to figure out DSA, a long storied technology that uses self-forming polymers to allow less light to sharply etch smaller features. If they figure out DSA, they will likely be ahead of TSMC. If not, it will just be more very expensive la…

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

> This is the industry roadmap from 2022: https://irds.ieee.org/images/files/pdf/2022/2022IRDS_Litho.p...

Very interesting document - lots of numbers in there for real feature sizes that I had not seen before (Table LITH-1).

And this snippet was particularly striking:

Chip making in Taiwan already uses as much as 10% of the island’s electricity.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#166

Post by hajile »

ahartmetz wrote: post #143
Rinzler89 wrote: post #85

Earlier quoted context omitted.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

>EUV was cracked More like it was started. There were a ton of gnarly problems left that took over ten years and billions of € to solve. Producing a few flashes of EUV and getting a few photons on the target is relatively easy. Producing a lot of EUV for a long time and getting a significant fraction (...like 1%) of the photons on the target is very hard.

EUV was supposed to ship in the early 2000s and the work on it started in earnest the 90s. It turned out that EUV is way harder than anyone imagined. The only reason we did stuff like immersion DUV was because we couldn’t get EUV to work.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#167

Post by bee_rider »

black_puppydog wrote: post #131
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Stupid beginner question: is MTr/mm² really the right thing to be looking at? Shouldn't it be more like mm²/MTr ? This feels kind of like these weird "miles per gallon" units, when "gallons per mile" is much more useful...

What’s the argument for either? They are, of course, equivalent… might as well pick the one where bigger=better.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#168

Post by bee_rider »

exe34 wrote: post #98
_heimdall wrote: post #48

Earlier quoted context omitted.

They're using the wrong units if we need to consider the nanometer as something other than a measure of distance.

Wait till you talk to theoretical physicists who set c=h-bar=1.

I don’t think they drop the dimensions, just the constants.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#169

Post by HarHarVeryFunny »

ajross wrote: post #159
HarHarVeryFunny wrote: post #74

Earlier quoted context omitted.

Intel is the one trying to catch up to TSMC, not vice versa! The link you give doesn't have any details of Intel's 18A process, including no indication of it innovating in any way, as opposed to TSMC with their "backside power delivery" which is going to be critical for power-hungry SOTA AI chips.

This isn't a comparison of shipping processes though, it's just roadmap products. And in fact until this announcement Intel was "ahead" of TSMC on the 2026 roadmap.

I can't see that going down too well on an earnings call.

"Well, yes, we're behind TSMC in technology, but in our dreams we're way ahead!"

Post reply on HN