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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#151

Post by robocat »

merb wrote: post #132
7thpower wrote: post #87

Earlier quoted context omitted.

Yes, generally one of the trends has been movement toward specialized coprocessors/accelerators. This was happening before the recent AI push and has picked up steam. If you think of an SOC, the chip in your phone, more and more of the real estate is being dedicated to specialized compute (AI accelerators, GPUs, etc. vs general purpose compute (CPU). At the enterprise scale, one of the big arguments NVIDIA has been m…

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

Reminiscent of the Java CPUs: Not even used for embedded (ironically the reason Java was created?). And not used at all by the massive Java compute needed for corporate software worldwide?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#152

Post by robocat »

kjkjadksj wrote: post #140
jjk166 wrote: post #125

Earlier quoted context omitted.

The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimization…

What about the effect of heat? More transistors per area equate a hotter chip, no?

More transistors switching I thought? It isn't about raw transistors e.g. memory isn't as power hungry as GPU?

Re: TSMC unveils 1.6nm process technology with backside power delivery

#153

Post by Detrytus »

blagie wrote: post #144
1oooqooq wrote: post #136

Earlier quoted context omitted.

now I'm even more confused. why start with Si if you're going to put a glass layer before anything else? why not start with glass right away?

Ergo, the TL;DR :) Even so, I oversimplified things a lot (a lot of the processes to leverage the silicon wafer, but some don't): https://en.wikipedia.org/wiki/Silicon_on_insulator One of the things to keep in mind is that a silicon wafer starts with a near-perfect silicon ingot crystal: https://en.wikipedia.org/wiki/Monocrystalline_silicon The level of purity and perfection there is a little bit crazy to conceive. I…

>> There are something like ≈100 billion transistors per IC for something like a high-end GPU, and a single failed transistor can destroy that fancy GPU.

No, it can't thanks to this fancy marketing strategy where you sell faulty GPUs at lower price, as lower-tier model.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#154

Post by merb »

choilive wrote: post #141
merb wrote: post #132

Earlier quoted context omitted.

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

I believe ARM has some instructions that is JavaScript specific so we're kinda in that direction already.

Yeah the https://developer.arm.com/documentation/dui0801/h/A64-Floati... but a full jit helper that is generalized is way way harder and as said will take a long time tobe generally available. Just look at wasmgc and that only has the minimum denominator.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#155

Post by [deleted] »

choilive wrote: post #141
merb wrote: post #132

Earlier quoted context omitted.

JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.

I believe ARM has some instructions that is JavaScript specific so we're kinda in that direction already.

[deleted]

Re: TSMC unveils 1.6nm process technology with backside power delivery

#156

Post by wtallis »

confused_boner wrote: post #122
Sysreq2 wrote: post #95

Earlier quoted context omitted.

The nomenclature for microchip manufacturing left reality a couple generations ago. Intel’s 14A process is not a true 14A half-pitch. It’s kind of like how they started naming CPUs off “performance equivalents” instead of using raw clock speed. And this isn’t just Intel. TSMC, Samsung, everyone is doing half-pitch equivalent naming now a days. This is the industry roadmap from 2022: https://irds.ieee.org/images/files…

would performance per watt be the right way to benchmark?

When comparing fab processes, you wouldn't want performance of a whole processor but rather the voltage vs frequency curves for the different transistor libraries offered by each fab process.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#157

Post by seastarer »

futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Translating 197 M/mm2 into the dimensions of a square, we get a dimension of 71nm. If we compute the "half-pitch", that's 35.5nm.

230 M/mm2 translates to 33nm "half-pitch".

Of course, transistors aren't square and aren't so densely packed, but these numbers are more real IMO.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#158

Post by alberth »

futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

> This 1.6nm process will put them around 230 MTr/mm2

Would it be that x2 (for front & back)?

E.g., 230 on front side and another 230 on back side = 460 MTr/mm2 TOTAL

Re: TSMC unveils 1.6nm process technology with backside power delivery

#159

Post by ajross »

HarHarVeryFunny wrote: post #74
654wak654 wrote: post #6

Sounds like a response to Intel's 18A process [0], which is also coming in 2026. [0] https://www.tomshardware.com/tech-industry/manufacturing/int...

Intel is the one trying to catch up to TSMC, not vice versa! The link you give doesn't have any details of Intel's 18A process, including no indication of it innovating in any way, as opposed to TSMC with their "backside power delivery" which is going to be critical for power-hungry SOTA AI chips.

This isn't a comparison of shipping processes though, it's just roadmap products. And in fact until this announcement Intel was "ahead" of TSMC on the 2026 roadmap.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#160

Post by Havoc »

audunw wrote: post #134
Havoc wrote: post #8

>1.6nm Gotta love how we now have fractions of a near meaningless metric.

The metric means what it has always meant: lower numbers mean higher transistor density on some area (the digital part) of the chip. What more do you want? It’s as meaningful as a single number ever could be. If you’re a consumer - if you don’t design chips - lower number means there’s some improvement somewhere. That’s all you need to know. It’s like horse powers on a car. The number doesn’t tell you everything abou…

>The metric means what it has always meant

That's just patently wrong.

The measurement used to refer to feature size [0]. It used to be a physical measurement of a thing in nanometers hence nm

Now it's a free for all marketing team names it whatever the fuck they want. That's why you get stuff like intel 10nm being equivalent to AMD 7nm. [1]. It's not real.

>Who cares?

You...else we wouldn't be having this discussion

[0] https://en.wikipedia.org/wiki/Semiconductor_device_fabricati...

[1] https://www.pcgamer.com/chipmaking-process-node-naming-lmc-p...

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