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TSMC unveils 1.6nm process technology with backside power delivery

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#101

Post by pjc50 »

AdamN wrote: post #78
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

There's still the question though of why they didn't do this decades ago - seems very obvious that this layout is better. What changed that made it possible only now and not earlier?

> why they didn't do this decades ago

You might as well ask why, since we can do it now, Shockley didn't simply start at 3nm. It's all a very long road of individual process techniques.

> You need very tiny wires through very tiny holes in locations very precisely aligned on both sides.

Key word here is "both sides". It has challenges similar to solder reflow on double sided boards: you need to ensure that work done on the first side isn't ruined/ruining work on the second side.

https://semiwiki.com/semiconductor-services/techinsights/288... seems to be a good description.

"The challenges with BPR are that you need a low resistance and reliable metal line that does not contaminate the Front End Of Line (FEOL). BPR is inserted early in the process flow and must stand up to all the heat of the device formation steps."

Contamination = metals used musn't "poison" the front-side chemistry. So they end up using tungsten rather than the more usual aluminium. (Copper is forbidden for similar chemistry reasons)

It also (obviously) adds a bunch of processing steps, each of which adds to the cost, more so than putting the rails on the front side.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#102

Post by gtirloni »

magicalhippo wrote: post #44
gtirloni wrote: post #29

> This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks Uh?

I imagine it's because AI and HPC processors are typically utilized much more fully than your regular desktop processor. A typical desktop CPU is designed to execute very varied and branch-heavy code. As such they have a lot of cache and a lot of logic transistors sitting idle at any given time, either waiting for memory or because the code is adding not multiplying for example. You can see that in the die shots like…

The needs of AI/HPC at the chip level weren't clear to me. Thanks for the insightful answer.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#103

Post by s3p »

Rinzler89 wrote: post #85
saganus wrote: post #69

Earlier quoted context omitted.

Do you know the name of the company that produces the EUV machine? is it ASML? It is my understanding that only ASML had cracked the EUV litography, but if there's another company out there, that would be an interesting development to watch.

>It is my understanding that only ASML had cracked the EUV litography Ackshually , EUV was cracked by Sandia Labs research in the US, with EUV light sources built by Cymer in the US. ASML was the only one allowed to license the tech and integrate it into their steppers after they bough Cymer in 2013. Hence why US has veto rights to whom Dutch based ASML can sell their EUV steppers to, as in not to China, despite ow m…

They don't need anyone else's money. Intel has bought all of TSMC's EUV and High-NA EUV machines for the next several years.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#104

Post by SAI_Peregrinus »

_heimdall wrote: post #48
blackoil wrote: post #20

Earlier quoted context omitted.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

They're using the wrong units if we need to consider the nanometer as something other than a measure of distance.

Think of them as "node metrics". 1.4 node metrics, not nanometers. They haven't referred to any distance in years, so make up your favorite backronym. Å can be Åwesomes, so 1.4 node metrics = 14 Åwesomes. Embrace nonsense, the chip makers did!

Re: TSMC unveils 1.6nm process technology with backside power delivery

#105

Post by thsksbd »

__alexs wrote: post #46
thsksbd wrote: post #40

Earlier quoted context omitted.

1.6 nm is 16 A. If they continue the BS for much longer, the "feature size" will be smaller than the lattice of Si.

You're the one calling it a feature size, not TSMC.

They're the ones specifying units.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#106

Post by [deleted] »

ReptileMan wrote: post #65
futureshock wrote: post #59

Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?

[deleted]

Re: TSMC unveils 1.6nm process technology with backside power delivery

#107

Post by s3p »

yau8edq12i wrote: post #86
misja111 wrote: post #72

Earlier quoted context omitted.

Nope that's what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is smaller than the size of a transistor. This means that when different manufacturers use a different transistor design, their 'nm' process could be the same but their transistor density different.

No, it's not even related to gate length or any kind of physical feature anymore. It's a purely marketing term. A "3 nm" node has a gate length around 16-18 nm.

OP isn't wrong. Once the switch was made from 2D to 3D gates, transistor numbering became "this is the performance you would expect if you COULD shrink a gate to x nm", and while it's inaccurate it lets people understand how differentiated a new generation is from the previous ones. It also lets them stay consistent with understanding the progression of chips over time as in most of the history of silicon the generations were defined by the gates' nm sizing.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#108

Post by maqp »

yau8edq12i wrote: post #86
misja111 wrote: post #72

Earlier quoted context omitted.

Nope that's what it meant a long time ago. Nowadays, the nm number represents the smallest possible element on the chip, typically the gate length, which is smaller than the size of a transistor. This means that when different manufacturers use a different transistor design, their 'nm' process could be the same but their transistor density different.

No, it's not even related to gate length or any kind of physical feature anymore. It's a purely marketing term. A "3 nm" node has a gate length around 16-18 nm.

I don't see it as an issue if the marketing term maintains the original context:

"how large a planar FET should be for the transistor density used in this process"

Is this the case, I'm not entirely sure. If it is, there be a better unit for this measurement, absolutely.

PLANETS: PLANar Equivalent Transistor Size

Or hire a marketing team to figure a good one.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#109

Post by s3p »

HarHarVeryFunny wrote: post #74
654wak654 wrote: post #6

Sounds like a response to Intel's 18A process [0], which is also coming in 2026. [0] https://www.tomshardware.com/tech-industry/manufacturing/int...

Intel is the one trying to catch up to TSMC, not vice versa! The link you give doesn't have any details of Intel's 18A process, including no indication of it innovating in any way, as opposed to TSMC with their "backside power delivery" which is going to be critical for power-hungry SOTA AI chips.

OP never said Intel wasn't trying to catch up. As far as backside power delivery, this is literally what Intel has been working on. It is called PowerVia.

https://www.intel.com/content/www/us/en/newsroom/news/powerv...

Re: TSMC unveils 1.6nm process technology with backside power delivery

#110

Post by SAI_Peregrinus »

pedrocr wrote: post #60
blagie wrote: post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

> You need very tiny wires through very tiny holes in locations very precisely aligned on both sides. Aligning things on the scale of nanometers is very, very hard. Do you need to align that precisely? Can't the power side have very large landing pads for the wires from the signal side to make it much easier?

Not big enough, they still need to fit the size of the transistors on the signal side.
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