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Calyx: Intermediate Language for Hardware Accelerators

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Re: Calyx: Intermediate Language for Hardware Accelerators

#21
post #3

https://calyxir.org/ shows me a Paper button where a click does nothing but grey it.

Odd, it works correctly for me: https://rachit.pl/files/pubs/calyx.pdf What platform/browser has this problem?

Chrome on Android for me. Works on Firefox on Android.

Re: Calyx: Intermediate Language for Hardware Accelerators

#22

Earlier quoted context omitted.

I think the developer did a great job for at least trying . I'm no hardware design expert, but the amount of work done shows. Plus it's reproducible research. If you're so sure about the quality and utility of the work done, you can get the artifacts, reproduce the toolchain, and write a nice rebuttal about it, and maybe even suggest improvements to the work done. Who knows. I think, failure is a way better outcome t…

It was not my intent to be discouraging towards the project, but rather than a frustration about a consistently misplaced attention from outsiders and science/research community.

"outsiders" can often bring a new perspective. There are many people who overlap both the hardware and software worlds (I consider myself one of them having started out in hardware and then moving over to the software side in EDA). Without those kinds of people you wouldn't have the kinds of EDA tools you have now.

> misplaced attention from outsiders and science/research community.

Come join the software side and work on the tools you want to see.

Re: Calyx: Intermediate Language for Hardware Accelerators

#23
My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.

I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.

That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."

A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.

There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].

1: https://www.chisel-lang.org

2: https://github.com/sarchlab/akita

Re: Calyx: Intermediate Language for Hardware Accelerators

#25
post #19
post #14

Earlier quoted context omitted.

do you have HTTP links blocked?

No e.g. reply on HN works.

But that's a relative link, so if you're using HN via HTTPS that will be an HTTPS link as well. Downloading the paper redirects you to http://rachit.pl/files/pubs/calyx.pdf, a plain HTTP link.

Re: Calyx: Intermediate Language for Hardware Accelerators

#26

Earlier quoted context omitted.

It was not my intent to be discouraging towards the project, but rather than a frustration about a consistently misplaced attention from outsiders and science/research community.

But again, this notion of "outsiders" is very gatekeepy. There have been substaintial successes in using high-level programming models for hardware design. The Google VCU paper explicitly mentions using such tools made them faster. All of these is enabled by people looking at problems with a fresh perspective

I don't have a horse in this race, and maybe the root comment came off as flippant and disparaging. But I'm not reading "outsiders" as being what you say "gatekeeping".

Maybe another perspective is that "outsiders" may not have the same view of the issue as experts in the field and may not (historically, in OP's experience) seem to want to work together with the experts to develop this view. Handwaving away complexities and not willing to get hands dirty is something I've seen as well so maybe I'm a bit more empathetic, but cold shoulders from "experts" towards newcomers is definitely a thing.

Both of which could help both sides - bring more depth to the fresh view of the "outsiders" and actually bring valuable freshness to the depth of the "experts".

Re: Calyx: Intermediate Language for Hardware Accelerators

#27
I'm always interested in new hardware-oriented DSLs, so great to see effort and work here.

rachitnigam, do you have any example designs of "significant" complexity? I looked over the paper and saw your 2x2 array example -- I'm curious if you make this something like 100x100 or n x m, can that be done in parameterizable way? What about control-structures like bits to enable / disable functionality, etc?

Also, do you provide a way to do things like arbitrary insert pipeline registers and let your tools track that?

One comment when comparing to Vivado HLS, fundamentally HLS breaks all problems down into CSP-style designs (whether you want that or not) and it takes a lot of experimentation with #pragmas to get a more optimal design. Not claiming Vivado HLS will beat your tool, but it's possible with some tuning to get a "better" design.

Re: Calyx: Intermediate Language for Hardware Accelerators

#28

Almost every couple of years (and once a decade for something "big") there is a new development in the area mostly driven either by clueless software guys that wandered outisde their turf into hardware territory, or some university chair that sits in the undefined limbo between hardware and software (usually doing something in the realm of CGRAs) that has to justify its existence by offering a PhD to some guy that wi…

The fact that calyx has both parallel as well as sequential blocks means that it is significantly ahead of most HLS languages. That is not a tiny difference, mind you. It is a gargantuan one.

Re: Calyx: Intermediate Language for Hardware Accelerators

#29
post #24

How does this compare to chisel?

From a glance: it seems like it is more specific for accelerators. Chisel deals in the general way, but Calyx seems to have primitives for wiring systolic arrays for example. If you plan to do an OoO CPU, choose Chisel. If you want to do a DSP or TPU, choose Calyx.

Re: Calyx: Intermediate Language for Hardware Accelerators

#30
post #19

Earlier quoted context omitted.

No e.g. reply on HN works.

But that's a relative link, so if you're using HN via HTTPS that will be an HTTPS link as well. Downloading the paper redirects you to http://rachit.pl/files/pubs/calyx.pdf , a plain HTTP link.

OK. Thanks.

But http://www.bbc.co.uk works.

http://rachit.pl/files/pubs/calyx.pdf fails. I suspect /PDF/.

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