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Calyx: Intermediate Language for Hardware Accelerators

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Re: Calyx: Intermediate Language for Hardware Accelerators

#11

Post by [deleted] »

UncleOxidant wrote: post #4
artemonster wrote: post #2

Almost every couple of years (and once a decade for something "big") there is a new development in the area mostly driven either by clueless software guys that wandered outisde their turf into hardware territory, or some university chair that sits in the undefined limbo between hardware and software (usually doing something in the realm of CGRAs) that has to justify its existence by offering a PhD to some guy that wi…

> Developing hardware is a solved problem. Has been for decades. So we should have just stuck with schematic capture, then? Why were HDLs and logic synthesis developed (by those pesky "clueless" software engineers)? To increase productivity. Current HLS can (especially in certain domains like DSP) increase productivity. Sure, I'll agree that some of the hardware oriented DSLs probably weren't all that necessary if yo…

[deleted]

Re: Calyx: Intermediate Language for Hardware Accelerators

#12

Post by artemonster »

chrisjj wrote: post #5
artemonster wrote: post #2

Almost every couple of years (and once a decade for something "big") there is a new development in the area mostly driven either by clueless software guys that wandered outisde their turf into hardware territory, or some university chair that sits in the undefined limbo between hardware and software (usually doing something in the realm of CGRAs) that has to justify its existence by offering a PhD to some guy that wi…

Check out 2.2 Optimizing Accelerator Designs High-level specifications of accelerators encode a treasure trove of control flow information that is lost when lowering to a registertransfer level (RTL) language.

Can you elaborate how is that information is helpful in any regard? I.e. resource scheduling, area optimization, timing?

Re: Calyx: Intermediate Language for Hardware Accelerators

#13

Post by bayindirh »

artemonster wrote: post #10
rachitnigam wrote: post #6

Earlier quoted context omitted.

Author of Calyx here. I always find these arguments quite reductive but will nonetheless entertain them. "Developing Hardware is a solved problem" For which audience specifically? Maybe if you consider giant teams at large corps pouring in millions. Is it a solved problem for hobbyists, students, people who're just curious? Most people who're curious about software can go play with it in 15 mins. For hardware, it's m…

Good luck! :)

I think the developer did a great job for at least trying. I'm no hardware design expert, but the amount of work done shows. Plus it's reproducible research. If you're so sure about the quality and utility of the work done, you can get the artifacts, reproduce the toolchain, and write a nice rebuttal about it, and maybe even suggest improvements to the work done. Who knows.

I think, failure is a way better outcome than not trying in the first place.

Re: Calyx: Intermediate Language for Hardware Accelerators

#15

Post by artemonster »

bayindirh wrote: post #13
artemonster wrote: post #10

Earlier quoted context omitted.

Good luck! :)

I think the developer did a great job for at least trying . I'm no hardware design expert, but the amount of work done shows. Plus it's reproducible research. If you're so sure about the quality and utility of the work done, you can get the artifacts, reproduce the toolchain, and write a nice rebuttal about it, and maybe even suggest improvements to the work done. Who knows. I think, failure is a way better outcome t…

It was not my intent to be discouraging towards the project, but rather than a frustration about a consistently misplaced attention from outsiders and science/research community.

Re: Calyx: Intermediate Language for Hardware Accelerators

#16

Post by rachitnigam »

artemonster wrote: post #15
bayindirh wrote: post #13

Earlier quoted context omitted.

I think the developer did a great job for at least trying . I'm no hardware design expert, but the amount of work done shows. Plus it's reproducible research. If you're so sure about the quality and utility of the work done, you can get the artifacts, reproduce the toolchain, and write a nice rebuttal about it, and maybe even suggest improvements to the work done. Who knows. I think, failure is a way better outcome t…

It was not my intent to be discouraging towards the project, but rather than a frustration about a consistently misplaced attention from outsiders and science/research community.

But again, this notion of "outsiders" is very gatekeepy. There have been substaintial successes in using high-level programming models for hardware design.

The Google VCU paper explicitly mentions using such tools made them faster. All of these is enabled by people looking at problems with a fresh perspective

Re: Calyx: Intermediate Language for Hardware Accelerators

#17

Post by rachitnigam »

buildbot wrote: post #9

Seems interesting - if I understand, this lets you get Verilog from a frontend you build. Can this be used to implement say a backend for pytorch? How does one link the generated verilog to software that can drive the design (in sim or actual FPGA/ASIC hardware)? Or is that left to you to build a driver separately for?

Author of Calyx here. Good question! Usually, you can use OpenCL based drivers to interface with standard memory interfaces on FPGAs.

ASICs require a lot more work by either packaging on the same chip as a processor or building IO interfaces for their own package.

Re: Calyx: Intermediate Language for Hardware Accelerators

#18

Post by chrisjj »

rachitnigam wrote: post #7
chrisjj wrote: post #3

https://calyxir.org/ shows me a Paper button where a click does nothing but grey it.

Odd, it works correctly for me: https://rachit.pl/files/pubs/calyx.pdf What platform/browser has this problem?

Android Chrome.

Re: Calyx: Intermediate Language for Hardware Accelerators

#20

Post by rachitnigam »

artemonster wrote: post #12
chrisjj wrote: post #5

Earlier quoted context omitted.

Check out 2.2 Optimizing Accelerator Designs High-level specifications of accelerators encode a treasure trove of control flow information that is lost when lowering to a registertransfer level (RTL) language.

Can you elaborate how is that information is helpful in any regard? I.e. resource scheduling, area optimization, timing?

All of those things. Most HLS tools use the CDFG to generate optimized resource bindings and area-aware optimizations.
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