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RISC-V Assembler: Arithmetic

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Re: RISC-V Assembler: Arithmetic

#21

Post by epcoa »

edgyquant wrote: post #20
epcoa wrote: post #18

Earlier quoted context omitted.

Machine code doesn’t have mnemonics either. What’s your point? There are assembly syntaxes with equal signs (The Itanium though ultimately a failure was not obscure and there are a handful of DSP ISAs that use this syntax). Not my cup of tea but your argument is specious. > Assembly is meant to be 1:1 with machine code, And that is nonsense as well. RISC-V is a perfect example as it has plenty of pseudo ops. (Or do y…

It isn’t my definition so your entire rant here is just being argumentative and defensive for no reason. Just because some fringe ISAs have equal signs in their assembler doesn’t change anything either. Assembly is meant to map directly to the way the machine code is written, and ran, so having [opcode] [operand(s)] makes perfect sense and quality of life/syntactic sugar beyond very simple things like variables (whic…

> fringe ISAs

Itanium fringe? You’re clueless and have no credibility.

We’re talking about an = instead of a , … you’re needlessly bringing up “crazy ASTs”, so much for being argumentative.

And defensive?

You seem mixed up, I’m not the one even advocating for the damn things. But your argument is ignorant and foolish.

> Assembly is meant to map directly to the way the machine code is written

This is just false.

https://github.com/netwide-assembler/nasm/blob/master/asm/as... Simple?

Re: RISC-V Assembler: Arithmetic

#22

Post by _a_a_a_ »

IshKebab wrote: post #8

> ProTip: Hexadecimal literals are prefixed with 0x. I love the idea that someone could get to this page and not already know that! Also this nicely highlights my pet peeve with assembly: add rd, rs1, rs2 # rd = rs1 + rs2 It's very difficult to remember which parameter is the destination etc. IMO it would be much nicer if assembly had just a little more syntax for that sort of thing. E.g. rd = add rs1, rs2 t0 = li 5…

  >  rd = add rs1, rs2
I dunno, how about

  rd = rs1 + rs2

Re: RISC-V Assembler: Arithmetic

#23

Post by snvzz »

sylware wrote: post #7
snvzz wrote: post #3

Earlier quoted context omitted.

I got into 68000 programming quite late (6yr ago), but I have been enjoying it (so far Amiga, Atari ST, rosco-m68k). It is a very programmer-friendly instruction set architecture. RISC-V I started playing with more recently (early 2023, thanks to VisionFive 2), and it feels like my old favorite (MIPS), without the baggage MIPS carried. It is a pleasure to work with this amount of GPRs and the comfortable alternative…

Yep, same, I am keeping an eye on Oasis, but to run powerful GPU drivers (much user space would have to be ported from c++ to hand written risc-v assembly, SDK included). Don't rush it though, concurrent access and memory coherence of device memory is still not finalized. I have been coding kind of a lot x64 recently, the limitation of 16 GPRs has been painful. I am sure that when I will crank up on rv64 assembly pro…

>In the other hand, I am not fond of the ABI register names

Why? They're simple substitution, and very helpful with following ABI.

>and the pseudo-instructions involving mini-compilation.

Again, why? These aren't specific to the assembler used, but rather, defined in the specification itself. This means they are reliable, and will always be there for as long as you use a RISC-V compliant assembler.

They are thus also the register names you will see in disassembler output, debuggers and other tools.

Also, you might be interested in this new RVA22+V board[0].

0. https://forum.banana-pi.org/t/leading-the-future-of-computin...

Re: RISC-V Assembler: Arithmetic

#24

Post by Pet_Ant »

edgyquant wrote: post #17
IshKebab wrote: post #8

> ProTip: Hexadecimal literals are prefixed with 0x. I love the idea that someone could get to this page and not already know that! Also this nicely highlights my pet peeve with assembly: add rd, rs1, rs2 # rd = rs1 + rs2 It's very difficult to remember which parameter is the destination etc. IMO it would be much nicer if assembly had just a little more syntax for that sort of thing. E.g. rd = add rs1, rs2 t0 = li 5…

Assembly is meant to be 1:1 with machine code, which makes writing an assembler extremely easy as long as you know the architecture. Machine code doesn’t have things like equal signs, it’s literally just a series of bytes (an opcode and operands) If you want equal signs, use C

I mean if you want to be 1:1 with machine code, then don't look at the "J" Jump or "B" Branch instruction formats where the constant value is split into pieces and packed in around the registers.

With a '=' all OP is asking for is the wee-est bit of grammar (no more than in some addressing modes in CISC assemblers) and to change the order of the registers, which isn't crazy since immediates are already split.

https://en.wikipedia.org/wiki/RISC-V#Design

PS- while the instruction formats look crazy in isolation, there is a nice symmetry between them and if you start thinking about instruction decoding in discrete logic, they are actually quite an elegant design.

PPS- there is also “High Level Assembly” https://en.m.wikipedia.org/wiki/High_Level_Assembly

Re: RISC-V Assembler: Arithmetic

#25

Post by snvzz »

throwaway71271 wrote: post #4

I love RISC-V assembler. I did a bit of x86 as stuff 20 years ago but hated it, now I wanted to teach my daughter some c and assembler and was thinking between arm and riscv, but riscv is just a joy to teach (I made a riscv assembler boardgame to help with the task https://punkx.org/overflow/ ) Recently I was rewatching Hackers(1995) and I also got excited about the same quote: > “RISC architecture is going to change…

Note this is an older (pre-ratification) cheatsheet.

You can tell because sbreak/scall. They are ebreak/ecall in the final version.

AIUI, the reason the name was changed is that they're not necessarily calls to the supervisor. E.g. they could be calls to machine mode, or the hypervisor. And some chips only implement M mode.

Re: RISC-V Assembler: Arithmetic

#26

Post by inkyoto »

_a_a_a_ wrote: post #22
IshKebab wrote: post #8

> ProTip: Hexadecimal literals are prefixed with 0x. I love the idea that someone could get to this page and not already know that! Also this nicely highlights my pet peeve with assembly: add rd, rs1, rs2 # rd = rs1 + rs2 It's very difficult to remember which parameter is the destination etc. IMO it would be much nicer if assembly had just a little more syntax for that sort of thing. E.g. rd = add rs1, rs2 t0 = li 5…

> rd = add rs1, rs2 I dunno, how about rd = rs1 + rs2

Because from the CPU perspective, «+» is ambiguous as there is not one «addition» but many:

- signed add

- unsigned add

- add and carry

There are a few others in other ISA', then there are the operand sizes (byte, half-word, word, long word etc) and the «+» operator does not capture the operand size nor the specifics whereas

- rd = rs1 addu8 rs2

makes the intention clear: «add the lower 8 bits from rs2 to rs1, don't set the sign bit when overflown and store the product in rd».

Moreover, the «+» operation is commutative and the CPU instructions are not, e.g.

- rd = rs + #10

and

- rd = #10 + rs

mean two completely different things for the CPU and the latter does not even have an encoding for it. The assembly processor is not the right place to place the smarts in to figure out the programmer's intention, either, as it is a very straightforward 1:1 assembly syntax to the ISA encoding translator.

Re: RISC-V Assembler: Arithmetic

#27

Post by brucehoult »

epcoa wrote: post #13
jcranmer wrote: post #12

Earlier quoted context omitted.

If you want fun, there's the x86 assembly syntax where the destination is the first register, and the x86 assembly syntax where the destination is the last register. One is the syntax as is used in official documentation (the Intel and AMD manuals), most reverse engineering tools, etc. The other is the syntax most commonly used in practice because it's what gcc defaults to and actually isn't documented (which gets in…

> and the x86 assembly syntax where the destination is the last register. ITYM AT&T :). The idea is that the basic grammar is common across architectures to help compiler backend authors. The historical reason for the ordering is because that’s how it was on the PDP-11, the “mother” assembly. And all AT&T/GNU versions preserve this ordering regardless of the vendor format. > The other is the syntax most commonly used…

> The historical reason for the ordering is because that’s how it was on the PDP-11

True, I think. I mean, that certainly was the case for PDP-11 and VAX asm. 68000 too (pretty much a 32 bit, 16 register PDP-11). Whether that was the actual reason is more debatable.

> And all AT&T/GNU versions preserve this ordering regardless of the vendor format.

False. GNU `as` puts the destination register first for all of Arm32, Arm64, MIPS, PowerPC, RISC-V. Every RISC ISA, as far as I know. Except for store instructions, where the source register is first.

Re: RISC-V Assembler: Arithmetic

#28

Post by brucehoult »

epcoa wrote: post #21
edgyquant wrote: post #20

Earlier quoted context omitted.

It isn’t my definition so your entire rant here is just being argumentative and defensive for no reason. Just because some fringe ISAs have equal signs in their assembler doesn’t change anything either. Assembly is meant to map directly to the way the machine code is written, and ran, so having [opcode] [operand(s)] makes perfect sense and quality of life/syntactic sugar beyond very simple things like variables (whic…

> fringe ISAs Itanium fringe? You’re clueless and have no credibility. We’re talking about an = instead of a , … you’re needlessly bringing up “crazy ASTs”, so much for being argumentative. And defensive? You seem mixed up, I’m not the one even advocating for the damn things. But your argument is ignorant and foolish. > Assembly is meant to map directly to the way the machine code is written This is just false. https…

> Itanium fringe? You’re clueless

Very fringe. A huge market failure. Hardware discontinued. Support removed in LLVM (2.6), and the Linux kernel (6.7). Still seems to be hanging on in GCC, though it was initially going to be deprecated in GCC 10.

One of the very few ISAs I've never actually seen a real machine of, let alone used. And I've worked professionally on i960 (Stratus fault-tolerant computer), which not many people can say. Not to mention of course PA-RISC and Alpha and Pr1me and DG Nova/Eclipse (and an M88000 PC) as well as common-as-mud (and which I own examples of) SPARC and MIPS.

Re: RISC-V Assembler: Arithmetic

#29

Post by _a_a_a_ »

inkyoto wrote: post #26
_a_a_a_ wrote: post #22

Earlier quoted context omitted.

> rd = add rs1, rs2 I dunno, how about rd = rs1 + rs2

Because from the CPU perspective, «+» is ambiguous as there is not one «addition» but many: - signed add - unsigned add - add and carry There are a few others in other ISA', then there are the operand sizes (byte, half-word, word, long word etc) and the «+» operator does not capture the operand size nor the specifics whereas - rd = rs1 addu8 rs2 makes the intention clear: «add the lower 8 bits from rs2 to rs1, don't…

Good post! ok, for

  rd = rs1 addu8 rs2
use

  rd = rs1 +u8 rs2
etc. The + stands out, more clearly indicating addition. (to me anyway)

As for commutativity of +, it's not necessarily true. It depends entirely on what underlying operation + denotes. It's perfectly reasonable to use it for string concatenation, and that clearly isn't commutative. But if it's not in the case of an ISA, that's fine, just have the assembler reject it.

Re: RISC-V Assembler: Arithmetic

#30

Post by Findecanor »

snvzz wrote: post #23
sylware wrote: post #7

Earlier quoted context omitted.

Yep, same, I am keeping an eye on Oasis, but to run powerful GPU drivers (much user space would have to be ported from c++ to hand written risc-v assembly, SDK included). Don't rush it though, concurrent access and memory coherence of device memory is still not finalized. I have been coding kind of a lot x64 recently, the limitation of 16 GPRs has been painful. I am sure that when I will crank up on rv64 assembly pro…

>In the other hand, I am not fond of the ABI register names Why? They're simple substitution, and very helpful with following ABI. >and the pseudo-instructions involving mini-compilation. Again, why? These aren't specific to the assembler used, but rather, defined in the specification itself. This means they are reliable, and will always be there for as long as you use a RISC-V compliant assembler. They are thus also…

The standard pseudo-instructions are not just standard. They express idioms that get treated differently, sometimes also by hardware.

For example `li` gets expanded by the assembler into `liu` and `addi` which on larger RISC-V cores get recognised and fused back into a single op. Using `xori` instead of `addi` would have had the same result but wouldn't get fused.

Next, some idioms get recognised and automatically assembled into "compressed" 16-bit instructions to save space. For example "mv rd,rs" and "addi rd, rs, 0" both get assembled into "c.mv rd,rs". And on a larger RISC-V core, "c.mv" could be only a register rename in the decoder, thus taking 0 cycles.

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